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| author | Mon P Wang <wangmp@apple.com> | 2008-08-28 21:04:05 +0000 |
|---|---|---|
| committer | Mon P Wang <wangmp@apple.com> | 2008-08-28 21:04:05 +0000 |
| commit | 5ad0bf658aa1e3df4b15b64647a6f91e0641c294 (patch) | |
| tree | 68852c95ff169ef1858e7b485a5f6f7e66c8d129 /lib/Target/PowerPC | |
| parent | a3f8b7a4ce8ab5c46d52077162851105a390a6ac (diff) | |
| download | external_llvm-5ad0bf658aa1e3df4b15b64647a6f91e0641c294.zip external_llvm-5ad0bf658aa1e3df4b15b64647a6f91e0641c294.tar.gz external_llvm-5ad0bf658aa1e3df4b15b64647a6f91e0641c294.tar.bz2 | |
In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55499 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 9472cee..5c69085 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2734,20 +2734,16 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { switch (CC) { default: break; // SETUO etc aren't handled by fsel. case ISD::SETULT: - case ISD::SETOLT: case ISD::SETLT: std::swap(TV, FV); // fsel is natively setge, swap operands for setlt - case ISD::SETUGE: case ISD::SETOGE: case ISD::SETGE: if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); case ISD::SETUGT: - case ISD::SETOGT: case ISD::SETGT: std::swap(TV, FV); // fsel is natively setge, swap operands for setlt - case ISD::SETULE: case ISD::SETOLE: case ISD::SETLE: if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits @@ -2760,13 +2756,11 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { switch (CC) { default: break; // SETUO etc aren't handled by fsel. case ISD::SETULT: - case ISD::SETOLT: case ISD::SETLT: Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); - case ISD::SETUGE: case ISD::SETOGE: case ISD::SETGE: Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); @@ -2774,13 +2768,11 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); case ISD::SETUGT: - case ISD::SETOGT: case ISD::SETGT: Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); - case ISD::SETULE: case ISD::SETOLE: case ISD::SETLE: Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); |