diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2007-07-19 01:14:50 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-07-19 01:14:50 +0000 |
| commit | 64d80e3387f328d21cd9cc06464b5de7861e3f27 (patch) | |
| tree | 203a9dfb41eba2fd8bd65a1e8bb80f73e36c0771 /lib/Target/PowerPC | |
| parent | 4558b807a2076e199bcb019f5edc9eabbc5922c1 (diff) | |
| download | external_llvm-64d80e3387f328d21cd9cc06464b5de7861e3f27.zip external_llvm-64d80e3387f328d21cd9cc06464b5de7861e3f27.tar.gz external_llvm-64d80e3387f328d21cd9cc06464b5de7861e3f27.tar.bz2 | |
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstr64Bit.td | 202 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrAltivec.td | 116 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 265 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 351 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.h | 4 |
6 files changed, 479 insertions, 463 deletions
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index a7e25cf..e20ea47 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -57,7 +57,7 @@ def HI48_64 : SDNodeXForm<imm, [{ // Pseudo instructions. // -def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; IMPLICIT_DEF_G8RC $rD", +def IMPLICIT_DEF_G8RC : Pseudo<(outs G8RC:$rD), (ins),"; IMPLICIT_DEF_G8RC $rD", [(set G8RC:$rD, (undef))]>; @@ -66,7 +66,7 @@ def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; IMPLICIT_DEF_G8RC $rD", // let Defs = [LR8] in - def MovePCtoLR8 : Pseudo<(ops piclabel:$label), "bl $label", []>, + def MovePCtoLR8 : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>, PPC970_Unit_BRU; // Macho ABI Calls. @@ -79,11 +79,11 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7, CR0,CR1,CR5,CR6,CR7] in { // Convenient aliases for call instructions def BL8_Macho : IForm<18, 0, 1, - (ops calltarget:$func, variable_ops), + (outs), (ins calltarget:$func, variable_ops), "bl $func", BrB, []>; // See Pat patterns below. def BLA8_Macho : IForm<18, 1, 1, - (ops aaddr:$func, variable_ops), + (outs), (ins aaddr:$func, variable_ops), "bla $func", BrB, [(PPCcall_Macho (i64 imm:$func))]>; } @@ -98,11 +98,11 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7, CR0,CR1,CR5,CR6,CR7] in { // Convenient aliases for call instructions def BL8_ELF : IForm<18, 0, 1, - (ops calltarget:$func, variable_ops), + (outs), (ins calltarget:$func, variable_ops), "bl $func", BrB, []>; // See Pat patterns below. def BLA8_ELF : IForm<18, 1, 1, - (ops aaddr:$func, variable_ops), + (outs), (ins aaddr:$func, variable_ops), "bla $func", BrB, [(PPCcall_ELF (i64 imm:$func))]>; } @@ -121,22 +121,26 @@ def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)), //===----------------------------------------------------------------------===// // 64-bit SPR manipulation instrs. -def MFCTR8 : XFXForm_1_ext<31, 339, 9, (ops G8RC:$rT), "mfctr $rT", SprMFSPR>, +def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), + "mfctr $rT", SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; let Pattern = [(PPCmtctr G8RC:$rS)] in { -def MTCTR8 : XFXForm_7_ext<31, 467, 9, (ops G8RC:$rS), "mtctr $rS", SprMTSPR>, +def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), + "mtctr $rS", SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } -def DYNALLOC8 : Pseudo<(ops G8RC:$result, G8RC:$negsize, memri:$fpsi), +def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi), "${:comment} DYNALLOC8 $result, $negsize, $fpsi", [(set G8RC:$result, (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>, Imp<[X1],[X1]>; -def MTLR8 : XFXForm_7_ext<31, 467, 8, (ops G8RC:$rS), "mtlr $rS", SprMTSPR>, +def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), + "mtlr $rS", SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; -def MFLR8 : XFXForm_1_ext<31, 339, 8, (ops G8RC:$rT), "mflr $rT", SprMFSPR>, +def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), + "mflr $rT", SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; @@ -147,187 +151,187 @@ def MFLR8 : XFXForm_1_ext<31, 339, 8, (ops G8RC:$rT), "mflr $rT", SprMFSPR>, let PPC970_Unit = 1 in { // FXU Operations. // Copies, extends, truncates. -def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB), +def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB), "or $rA, $rS, $rB", IntGeneral, []>; -def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB), +def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB), "or $rA, $rS, $rB", IntGeneral, []>; -def LI8 : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm), +def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), "li $rD, $imm", IntGeneral, [(set G8RC:$rD, immSExt16:$imm)]>; -def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm), +def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), "lis $rD, $imm", IntGeneral, [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; // Logical ops. -def NAND8: XForm_6<31, 476, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "nand $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; -def AND8 : XForm_6<31, 28, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "and $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; -def ANDC8: XForm_6<31, 60, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "andc $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; -def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "or $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; -def NOR8 : XForm_6<31, 124, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "nor $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; -def ORC8 : XForm_6<31, 412, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "orc $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; -def EQV8 : XForm_6<31, 284, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "eqv $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; -def XOR8 : XForm_6<31, 316, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "xor $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; // Logical ops with immediate. -def ANDIo8 : DForm_4<28, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), +def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), "andi. $dst, $src1, $src2", IntGeneral, [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, isDOT; -def ANDISo8 : DForm_4<29, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), +def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), "andis. $dst, $src1, $src2", IntGeneral, [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, isDOT; -def ORI8 : DForm_4<24, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), +def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), "ori $dst, $src1, $src2", IntGeneral, [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; -def ORIS8 : DForm_4<25, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), +def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), "oris $dst, $src1, $src2", IntGeneral, [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; -def XORI8 : DForm_4<26, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), +def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), "xori $dst, $src1, $src2", IntGeneral, [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; -def XORIS8 : DForm_4<27, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), +def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), "xoris $dst, $src1, $src2", IntGeneral, [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; -def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "add $rT, $rA, $rB", IntGeneral, [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; -def ADDC8 : XOForm_1<31, 10, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "addc $rT, $rA, $rB", IntGeneral, [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, PPC970_DGroup_Cracked; -def ADDE8 : XOForm_1<31, 138, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "adde $rT, $rA, $rB", IntGeneral, [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; -def ADDI8 : DForm_2<14, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm), +def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), "addi $rD, $rA, $imm", IntGeneral, [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; -def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm), +def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm), "addis $rD, $rA, $imm", IntGeneral, [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; -def SUBFIC8: DForm_2< 8, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm), +def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), "subfic $rD, $rA, $imm", IntGeneral, [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; -def SUBF8 : XOForm_1<31, 40, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "subf $rT, $rA, $rB", IntGeneral, [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; -def SUBFC8 : XOForm_1<31, 8, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "subfc $rT, $rA, $rB", IntGeneral, [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, PPC970_DGroup_Cracked; -def SUBFE8 : XOForm_1<31, 136, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "subfe $rT, $rA, $rB", IntGeneral, [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; -def ADDME8 : XOForm_3<31, 234, 0, (ops G8RC:$rT, G8RC:$rA), +def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), "addme $rT, $rA", IntGeneral, [(set G8RC:$rT, (adde G8RC:$rA, immAllOnes))]>; -def ADDZE8 : XOForm_3<31, 202, 0, (ops G8RC:$rT, G8RC:$rA), +def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), "addze $rT, $rA", IntGeneral, [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; -def NEG8 : XOForm_3<31, 104, 0, (ops G8RC:$rT, G8RC:$rA), +def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), "neg $rT, $rA", IntGeneral, [(set G8RC:$rT, (ineg G8RC:$rA))]>; -def SUBFME8 : XOForm_3<31, 232, 0, (ops G8RC:$rT, G8RC:$rA), +def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), "subfme $rT, $rA", IntGeneral, [(set G8RC:$rT, (sube immAllOnes, G8RC:$rA))]>; -def SUBFZE8 : XOForm_3<31, 200, 0, (ops G8RC:$rT, G8RC:$rA), +def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), "subfze $rT, $rA", IntGeneral, [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; -def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "mulhd $rT, $rA, $rB", IntMulHW, [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; -def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "mulhdu $rT, $rA, $rB", IntMulHWU, [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; -def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB), +def CMPD : XForm_16_ext<31, 0, (outs), (ins CRRC:$crD, G8RC:$rA, G8RC:$rB), "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; -def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB), +def CMPLD : XForm_16_ext<31, 32, (outs), (ins CRRC:$crD, G8RC:$rA, G8RC:$rB), "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; -def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, G8RC:$rA, s16imm:$imm), +def CMPDI : DForm_5_ext<11, (outs), (ins CRRC:$crD, G8RC:$rA, s16imm:$imm), "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; -def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, G8RC:$src1, u16imm:$src2), +def CMPLDI : DForm_6_ext<10, (outs), (ins CRRC:$dst, G8RC:$src1, u16imm:$src2), "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; -def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB), +def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), "sld $rA, $rS, $rB", IntRotateD, [(set G8RC:$rA, (shl G8RC:$rS, GPRC:$rB))]>, isPPC64; -def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB), +def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), "srd $rA, $rS, $rB", IntRotateD, [(set G8RC:$rA, (srl G8RC:$rS, GPRC:$rB))]>, isPPC64; -def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB), +def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), "srad $rA, $rS, $rB", IntRotateD, [(set G8RC:$rA, (sra G8RC:$rS, GPRC:$rB))]>, isPPC64; -def EXTSB8 : XForm_11<31, 954, (ops G8RC:$rA, G8RC:$rS), +def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), "extsb $rA, $rS", IntGeneral, [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; -def EXTSH8 : XForm_11<31, 922, (ops G8RC:$rA, G8RC:$rS), +def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), "extsh $rA, $rS", IntGeneral, [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; -def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS), +def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), "extsw $rA, $rS", IntGeneral, [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. -def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS), +def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), "extsw $rA, $rS", IntGeneral, [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; -def EXTSW_32_64 : XForm_11<31, 986, (ops G8RC:$rA, GPRC:$rS), +def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), "extsw $rA, $rS", IntGeneral, [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; -def SRADI : XSForm_1<31, 413, (ops G8RC:$rA, G8RC:$rS, u6imm:$SH), +def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), "sradi $rA, $rS, $SH", IntRotateD, [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; -def CNTLZD : XForm_11<31, 58, (ops G8RC:$rA, G8RC:$rS), +def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), "cntlzd $rA, $rS", IntGeneral, [(set G8RC:$rA, (ctlz G8RC:$rS))]>; -def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "divd $rT, $rA, $rB", IntDivD, [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, PPC970_DGroup_First, PPC970_DGroup_Cracked; -def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "divdu $rT, $rA, $rB", IntDivD, [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, PPC970_DGroup_First, PPC970_DGroup_Cracked; -def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "mulld $rT, $rA, $rB", IntMulHD, [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; let isCommutable = 1 in { def RLDIMI : MDForm_1<30, 3, - (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), + (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), "rldimi $rA, $rS, $SH, $MB", IntRotateD, []>, isPPC64, RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; @@ -335,11 +339,11 @@ def RLDIMI : MDForm_1<30, 3, // Rotate instructions. def RLDICL : MDForm_1<30, 0, - (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB), + (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB), "rldicl $rA, $rS, $SH, $MB", IntRotateD, []>, isPPC64; def RLDICR : MDForm_1<30, 1, - (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME), + (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME), "rldicr $rA, $rS, $SH, $ME", IntRotateD, []>, isPPC64; } // End FXU Operations. @@ -352,25 +356,25 @@ def RLDICR : MDForm_1<30, 1, // Sign extending loads. let isLoad = 1, PPC970_Unit = 2 in { -def LHA8: DForm_1<42, (ops G8RC:$rD, memri:$src), +def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), "lha $rD, $src", LdStLHA, [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, PPC970_DGroup_Cracked; -def LWA : DSForm_1<58, 2, (ops G8RC:$rD, memrix:$src), +def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), "lwa $rD, $src", LdStLWA, [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, PPC970_DGroup_Cracked; -def LHAX8: XForm_1<31, 343, (ops G8RC:$rD, memrr:$src), +def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), "lhax $rD, $src", LdStLHA, [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, PPC970_DGroup_Cracked; -def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src), +def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), "lwax $rD, $src", LdStLHA, [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, PPC970_DGroup_Cracked; // Update forms. -def LHAU8 : DForm_1<43, (ops G8RC:$rD, ptr_rc:$ea_result, symbolLo:$disp, +def LHAU8 : DForm_1<43, (outs G8RC:$rD), (ins ptr_rc:$ea_result, symbolLo:$disp, ptr_rc:$rA), "lhau $rD, $disp($rA)", LdStGeneral, []>, RegConstraint<"$rA = $ea_result">, @@ -381,37 +385,37 @@ def LHAU8 : DForm_1<43, (ops G8RC:$rD, ptr_rc:$ea_result, symbolLo:$disp, // Zero extending loads. let isLoad = 1, PPC970_Unit = 2 in { -def LBZ8 : DForm_1<34, (ops G8RC:$rD, memri:$src), +def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), "lbz $rD, $src", LdStGeneral, [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; -def LHZ8 : DForm_1<40, (ops G8RC:$rD, memri:$src), +def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), "lhz $rD, $src", LdStGeneral, [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; -def LWZ8 : DForm_1<32, (ops G8RC:$rD, memri:$src), +def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), "lwz $rD, $src", LdStGeneral, [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; -def LBZX8 : XForm_1<31, 87, (ops G8RC:$rD, memrr:$src), +def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), "lbzx $rD, $src", LdStGeneral, [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; -def LHZX8 : XForm_1<31, 279, (ops G8RC:$rD, memrr:$src), +def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), "lhzx $rD, $src", LdStGeneral, [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; -def LWZX8 : XForm_1<31, 23, (ops G8RC:$rD, memrr:$src), +def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), "lwzx $rD, $src", LdStGeneral, [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; // Update forms. -def LBZU8 : DForm_1<35, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr), +def LBZU8 : DForm_1<35, (outs G8RC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lbzu $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LHZU8 : DForm_1<41, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr), +def LHZU8 : DForm_1<41, (outs G8RC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lhzu $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LWZU8 : DForm_1<33, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr), +def LWZU8 : DForm_1<33, (outs G8RC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lwzu $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; @@ -420,14 +424,14 @@ def LWZU8 : DForm_1<33, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr), // Full 8-byte loads. let isLoad = 1, PPC970_Unit = 2 in { -def LD : DSForm_1<58, 0, (ops G8RC:$rD, memrix:$src), +def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), "ld $rD, $src", LdStLD, [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; -def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src), +def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), "ldx $rD, $src", LdStLD, [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; -def LDU : DSForm_1<58, 1, (ops G8RC:$rD, ptr_rc:$ea_result, memrix:$addr), +def LDU : DSForm_1<58, 1, (outs G8RC:$rD), (ins ptr_rc:$ea_result, memrix:$addr), "ldu $rD, $addr", LdStLD, []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, NoEncode<"$ea_result">; @@ -436,32 +440,32 @@ def LDU : DSForm_1<58, 1, (ops G8RC:$rD, ptr_rc:$ea_result, memrix:$addr), let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Truncating stores. -def STB8 : DForm_1<38, (ops G8RC:$rS, memri:$src), +def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), "stb $rS, $src", LdStGeneral, [(truncstorei8 G8RC:$rS, iaddr:$src)]>; -def STH8 : DForm_1<44, (ops G8RC:$rS, memri:$src), +def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), "sth $rS, $src", LdStGeneral, [(truncstorei16 G8RC:$rS, iaddr:$src)]>; -def STW8 : DForm_1<36, (ops G8RC:$rS, memri:$src), +def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), "stw $rS, $src", LdStGeneral, [(truncstorei32 G8RC:$rS, iaddr:$src)]>; -def STBX8 : XForm_8<31, 215, (ops G8RC:$rS, memrr:$dst), +def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), "stbx $rS, $dst", LdStGeneral, [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, PPC970_DGroup_Cracked; -def STHX8 : XForm_8<31, 407, (ops G8RC:$rS, memrr:$dst), +def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), "sthx $rS, $dst", LdStGeneral, [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, PPC970_DGroup_Cracked; -def STWX8 : XForm_8<31, 151, (ops G8RC:$rS, memrr:$dst), +def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), "stwx $rS, $dst", LdStGeneral, [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, PPC970_DGroup_Cracked; // Normal 8-byte stores. -def STD : DSForm_1<62, 0, (ops G8RC:$rS, memrix:$dst), +def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), "std $rS, $dst", LdStSTD, [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; -def STDX : XForm_8<31, 149, (ops G8RC:$rS, memrr:$dst), +def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), "stdx $rS, $dst", LdStSTD, [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, PPC970_DGroup_Cracked; @@ -469,21 +473,21 @@ def STDX : XForm_8<31, 149, (ops G8RC:$rS, memrr:$dst), let isStore = 1, PPC970_Unit = 2 in { -def STBU8 : DForm_1<38, (ops ptr_rc:$ea_res, G8RC:$rS, +def STBU8 : DForm_1<38, (outs), (ins ptr_rc:$ea_res, G8RC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "stbu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff))]>, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; -def STHU8 : DForm_1<45, (ops ptr_rc:$ea_res, G8RC:$rS, +def STHU8 : DForm_1<45, (outs), (ins ptr_rc:$ea_res, G8RC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "sthu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff))]>, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; -def STWU8 : DForm_1<37, (ops ptr_rc:$ea_res, G8RC:$rS, +def STWU8 : DForm_1<37, (outs), (ins ptr_rc:$ea_res, G8RC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "stwu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, @@ -491,7 +495,7 @@ def STWU8 : DForm_1<37, (ops ptr_rc:$ea_res, G8RC:$rS, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; -def STDU : DSForm_1<62, 1, (ops ptr_rc:$ea_res, G8RC:$rS, +def STDU : DSForm_1<62, 1, (outs), (ins ptr_rc:$ea_res, G8RC:$rS, s16immX4:$ptroff, ptr_rc:$ptrreg), "stdu $rS, $ptroff($ptrreg)", LdStSTD, [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, @@ -503,16 +507,16 @@ def STDU : DSForm_1<62, 1, (ops ptr_rc:$ea_res, G8RC:$rS, let isStore = 1, noResults = 1, PPC970_Unit = 2 in { -def STDUX : XForm_8<31, 181, (ops G8RC:$rS, memrr:$dst), +def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst), "stdux $rS, $dst", LdStSTD, []>, isPPC64; // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. -def STD_32 : DSForm_1<62, 0, (ops GPRC:$rT, memrix:$dst), +def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), "std $rT, $dst", LdStSTD, [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; -def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst), +def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), "stdx $rT, $dst", LdStSTD, [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, PPC970_DGroup_Cracked; @@ -526,10 +530,10 @@ def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst), let PPC970_Unit = 3 in { // FPU Operations. -def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB), +def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), "fcfid $frD, $frB", FPGeneral, [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; -def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB), +def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), "fctidz $frD, $frB", FPGeneral, [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; } diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td index 8a2f255..47a470c 100644 --- a/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/lib/Target/PowerPC/PPCInstrAltivec.td @@ -138,97 +138,97 @@ def vecspltisw : PatLeaf<(build_vector), [{ // VA1a_Int - A VAForm_1a intrinsic definition. class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID> - : VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), + : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC), !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>; // VX1_Int - A VXForm_1 intrinsic definition. class VX1_Int<bits<11> xo, string opc, Intrinsic IntID> - : VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), !strconcat(opc, " $vD, $vA, $vB"), VecFP, [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>; // VX2_Int - A VXForm_2 intrinsic definition. class VX2_Int<bits<11> xo, string opc, Intrinsic IntID> - : VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB), + : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB), !strconcat(opc, " $vD, $vB"), VecFP, [(set VRRC:$vD, (IntID VRRC:$vB))]>; //===----------------------------------------------------------------------===// // Instruction Definitions. -def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; IMPLICIT_DEF_VRRC $rD", +def IMPLICIT_DEF_VRRC : Pseudo<(outs VRRC:$rD), (ins),"; IMPLICIT_DEF_VRRC $rD", [(set VRRC:$rD, (v4i32 (undef)))]>; let noResults = 1 in { -def DSS : DSS_Form<822, (ops u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), +def DSS : DSS_Form<822, (outs), (ins u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), "dss $STRM, $A", LdStGeneral /*FIXME*/, []>; -def DST : DSS_Form<342, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB), +def DST : DSS_Form<342, (outs), (ins u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB), "dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>; -def DSTST : DSS_Form<374, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB), +def DSTST : DSS_Form<374, (outs), (ins u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB), "dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>; } -def MFVSCR : VXForm_4<1540, (ops VRRC:$vD), +def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins), "mfvcr $vD", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>; -def MTVSCR : VXForm_5<1604, (ops VRRC:$vB), +def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB), "mtvcr $vB", LdStGeneral, [(int_ppc_altivec_mtvscr VRRC:$vB)]>; let isLoad = 1, PPC970_Unit = 2 in { // Loads. -def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src), +def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src), "lvebx $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; -def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src), +def LVEHX: XForm_1<31, 39, (outs VRRC:$vD), (ins memrr:$src), "lvehx $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; -def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src), +def LVEWX: XForm_1<31, 71, (outs VRRC:$vD), (ins memrr:$src), "lvewx $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; -def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src), +def LVX : XForm_1<31, 103, (outs VRRC:$vD), (ins memrr:$src), "lvx $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; -def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src), +def LVXL : XForm_1<31, 359, (outs VRRC:$vD), (ins memrr:$src), "lvxl $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; } -def LVSL : XForm_1<31, 6, (ops VRRC:$vD, memrr:$src), +def LVSL : XForm_1<31, 6, (outs VRRC:$vD), (ins memrr:$src), "lvsl $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, PPC970_Unit_LSU; -def LVSR : XForm_1<31, 38, (ops VRRC:$vD, memrr:$src), +def LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src), "lvsr $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, PPC970_Unit_LSU; let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores. -def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst), +def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst), "stvebx $rS, $dst", LdStGeneral, [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>; -def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst), +def STVEHX: XForm_8<31, 167, (outs), (ins VRRC:$rS, memrr:$dst), "stvehx $rS, $dst", LdStGeneral, [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>; -def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst), +def STVEWX: XForm_8<31, 199, (outs), (ins VRRC:$rS, memrr:$dst), "stvewx $rS, $dst", LdStGeneral, [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>; -def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst), +def STVX : XForm_8<31, 231, (outs), (ins VRRC:$rS, memrr:$dst), "stvx $rS, $dst", LdStGeneral, [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>; -def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst), +def STVXL : XForm_8<31, 487, (outs), (ins VRRC:$rS, memrr:$dst), "stvxl $rS, $dst", LdStGeneral, [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>; } let PPC970_Unit = 5 in { // VALU Operations. // VA-Form instructions. 3-input AltiVec ops. -def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB), +def VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), "vmaddfp $vD, $vA, $vC, $vB", VecFP, [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC), VRRC:$vB))]>, Requires<[FPContractions]>; -def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB), +def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), "vnmsubfp $vD, $vA, $vC, $vB", VecFP, [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC), VRRC:$vB)))]>, @@ -241,24 +241,24 @@ def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>; def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>; // Shuffles. -def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH), +def VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH), "vsldoi $vD, $vA, $vB, $SH", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VSLDOI_shuffle_mask:$SH))]>; // VX-Form instructions. AltiVec arithmetic ops. -def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vaddfp $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>; -def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VADDUBM : VXForm_1<0, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vaddubm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>; -def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VADDUHM : VXForm_1<64, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vadduhm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>; -def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VADDUWM : VXForm_1<128, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vadduwm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>; @@ -271,26 +271,26 @@ def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>; def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>; -def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VAND : VXForm_1<1028, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vand $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>; -def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VANDC : VXForm_1<1092, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vandc $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>; -def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +def VCFSX : VXForm_1<842, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), "vcfsx $vD, $vB, $UIMM", VecFP, [(set VRRC:$vD, (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>; -def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +def VCFUX : VXForm_1<778, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), "vcfux $vD, $vB, $UIMM", VecFP, [(set VRRC:$vD, (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>; -def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +def VCTSXS : VXForm_1<970, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), "vctsxs $vD, $vB, $UIMM", VecFP, [(set VRRC:$vD, (int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>; -def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +def VCTUXS : VXForm_1<906, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), "vctuxs $vD, $vB, $UIMM", VecFP, [(set VRRC:$vD, (int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>; @@ -319,27 +319,27 @@ def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>; def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>; def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>; -def VMRGHB : VXForm_1< 12, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vmrghb $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VMRGHB_shuffle_mask))]>; -def VMRGHH : VXForm_1< 76, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vmrghh $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VMRGHH_shuffle_mask))]>; -def VMRGHW : VXForm_1<140, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vmrghw $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VMRGHW_shuffle_mask))]>; -def VMRGLB : VXForm_1<268, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vmrglb $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VMRGLB_shuffle_mask))]>; -def VMRGLH : VXForm_1<332, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vmrglh $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VMRGLH_shuffle_mask))]>; -def VMRGLW : VXForm_1<396, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vmrglw $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VMRGLW_shuffle_mask))]>; @@ -369,16 +369,16 @@ def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>; -def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VSUBFP : VXForm_1<74, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vsubfp $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; -def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VSUBUBM : VXForm_1<1024, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vsububm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>; -def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VSUBUHM : VXForm_1<1088, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vsubuhm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>; -def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VSUBUWM : VXForm_1<1152, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vsubuwm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>; @@ -394,13 +394,13 @@ def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>; def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>; def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>; -def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VNOR : VXForm_1<1284, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vnor $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>; -def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VOR : VXForm_1<1156, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vor $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>; -def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VXOR : VXForm_1<1220, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vxor $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>; @@ -414,15 +414,15 @@ def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>; def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>; def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>; -def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), "vspltb $vD, $vB, $UIMM", VecPerm, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef), VSPLTB_shuffle_mask:$UIMM))]>; -def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), "vsplth $vD, $vB, $UIMM", VecPerm, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef), VSPLTH_shuffle_mask:$UIMM))]>; -def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), "vspltw $vD, $vB, $UIMM", VecPerm, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef), VSPLTW_shuffle_mask:$UIMM))]>; @@ -437,13 +437,13 @@ def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>; def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>; -def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM), +def VSPLTISB : VXForm_3<780, (outs VRRC:$vD), (ins s5imm:$SIMM), "vspltisb $vD, $SIMM", VecPerm, [(set VRRC:$vD, (v16i8 vecspltisb:$SIMM))]>; -def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM), +def VSPLTISH : VXForm_3<844, (outs VRRC:$vD), (ins s5imm:$SIMM), "vspltish $vD, $SIMM", VecPerm, [(set VRRC:$vD, (v8i16 vecspltish:$SIMM))]>; -def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM), +def VSPLTISW : VXForm_3<908, (outs VRRC:$vD), (ins s5imm:$SIMM), "vspltisw $vD, $SIMM", VecPerm, [(set VRRC:$vD, (v4i32 vecspltisw:$SIMM))]>; @@ -453,12 +453,12 @@ def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>; def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>; def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>; def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>; -def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vpkuhum $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VPKUHUM_shuffle_mask))]>; def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>; -def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vpkuwum $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VPKUWUM_shuffle_mask))]>; @@ -476,10 +476,10 @@ def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>; // Altivec Comparisons. class VCMP<bits<10> xo, string asmstr, ValueType Ty> - : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare, + : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>; class VCMPo<bits<10> xo, string asmstr, ValueType Ty> - : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare, + : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> { let Defs = [CR6]; let RC = 1; @@ -519,7 +519,7 @@ def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; -def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD), +def V_SET0 : VXForm_setzero<1220, (outs VRRC:$vD), (ins), "vxor $vD, $vD, $vD", VecFP, [(set VRRC:$vD, (v4i32 immAllZerosV))]>; } diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 6a4a59b..865320c 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -11,7 +11,7 @@ // // PowerPC instruction formats -class I<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> +class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> : Instruction { field bits<32> Inst; @@ -20,7 +20,8 @@ class I<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> let Name = ""; let Namespace = "PPC"; let Inst{0-5} = opcode; - let OperandList = OL; + let OutOperandList = OOL; + let InOperandList = IOL; let AsmString = asmstr; let Itinerary = itin; @@ -48,9 +49,9 @@ class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } // 1.7.1 I-Form -class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr, +class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { let Pattern = pattern; bits<24> LI; @@ -60,8 +61,8 @@ class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr, } // 1.7.2 B-Form -class BForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr> - : I<opcode, OL, asmstr, BrB> { +class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> + : I<opcode, OOL, IOL, asmstr, BrB> { bits<7> BIBO; // 2 bits of BI and 5 bits of BO. bits<3> CR; bits<14> BD; @@ -79,9 +80,9 @@ class BForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr> // 1.7.4 D-Form -class DForm_base<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, - list<dag> pattern> - : I<opcode, OL, asmstr, itin> { +class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> A; bits<5> B; bits<16> C; @@ -93,9 +94,9 @@ class DForm_base<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, let Inst{16-31} = C; } -class DForm_1<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, - list<dag> pattern> - : I<opcode, OL, asmstr, itin> { +class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> A; bits<16> C; bits<5> B; @@ -107,13 +108,13 @@ class DForm_1<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, let Inst{16-31} = C; } -class DForm_2<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, - list<dag> pattern> - : DForm_base<opcode, OL, asmstr, itin, pattern>; +class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>; -class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, - list<dag> pattern> - : I<opcode, OL, asmstr, itin> { +class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> A; bits<16> B; @@ -124,9 +125,9 @@ class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, let Inst{16-31} = B; } -class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, - list<dag> pattern> - : I<opcode, OL, asmstr, itin> { +class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> B; bits<5> A; bits<16> C; @@ -138,16 +139,17 @@ class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, let Inst{16-31} = C; } -class DForm_4_zero<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, - list<dag> pattern> - : DForm_1<opcode, OL, asmstr, itin, pattern> { +class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { let A = 0; let B = 0; let C = 0; } -class DForm_5<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { +class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin> + : I<opcode, OOL, IOL, asmstr, itin> { bits<3> BF; bits<1> L; bits<5> RA; @@ -160,24 +162,27 @@ class DForm_5<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> let Inst{16-31} = I; } -class DForm_5_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> - : DForm_5<opcode, OL, asmstr, itin> { +class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin> + : DForm_5<opcode, OOL, IOL, asmstr, itin> { let L = PPC64; } -class DForm_6<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> - : DForm_5<opcode, OL, asmstr, itin>; +class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin> + : DForm_5<opcode, OOL, IOL, asmstr, itin>; -class DForm_6_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> - : DForm_6<opcode, OL, asmstr, itin> { +class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin> + : DForm_6<opcode, OOL, IOL, asmstr, itin> { let L = PPC64; } // 1.7.5 DS-Form -class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr, +class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> RST; bits<14> DS; bits<5> RA; @@ -191,9 +196,9 @@ class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr, } // 1.7.6 X-Form -class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> RST; bits<5> A; bits<5> B; @@ -212,9 +217,9 @@ class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OL, string asmstr, // This is the same as XForm_base_r3xo, but the first two operands are swapped // when code is emitted. class XForm_base_r3xo_swapped - <bits<6> opcode, bits<10> xo, dag OL, string asmstr, + <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> A; bits<5> RST; bits<5> B; @@ -229,36 +234,36 @@ class XForm_base_r3xo_swapped } -class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern>; + : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; -class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> { + : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { let Pattern = pattern; } -class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern>; + : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; -class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> { + : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { let Pattern = pattern; } -class XForm_11<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> { + : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { let B = 0; let Pattern = pattern; } -class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<3> BF; bits<1> L; bits<5> RA; @@ -273,15 +278,15 @@ class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } -class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : XForm_16<opcode, xo, OL, asmstr, itin> { + : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { let L = PPC64; } -class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<3> BF; bits<5> FRA; bits<5> FRB; @@ -294,26 +299,26 @@ class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } -class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> { + : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { } -class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> { + : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { let A = 0; } -class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> { + : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { } // DCB_Form - Form X instruction, used for dcb* instructions. -class DCB_Form<bits<10> xo, bits<5> immfield, dag OL, string asmstr, +class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<31, OL, asmstr, itin> { + : I<31, OOL, IOL, asmstr, itin> { bits<5> A; bits<5> B; @@ -328,9 +333,9 @@ class DCB_Form<bits<10> xo, bits<5> immfield, dag OL, string asmstr, // DSS_Form - Form X instruction, used for altivec dss* instructions. -class DSS_Form<bits<10> xo, dag OL, string asmstr, +class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<31, OL, asmstr, itin> { + : I<31, OOL, IOL, asmstr, itin> { bits<1> T; bits<2> STRM; bits<5> A; @@ -348,9 +353,9 @@ class DSS_Form<bits<10> xo, dag OL, string asmstr, } // 1.7.7 XL-Form -class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> CRD; bits<5> CRA; bits<5> CRB; @@ -364,9 +369,9 @@ class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } -class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> CRD; let Pattern = pattern; @@ -378,9 +383,9 @@ class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } -class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OL, string asmstr, +class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> BO; bits<5> BI; bits<2> BH; @@ -396,8 +401,8 @@ class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OL, string asmstr, } class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, - dag OL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XLForm_2<opcode, xo, lk, OL, asmstr, itin, pattern> { + dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> + : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { bits<7> BIBO; // 2 bits of BI and 5 bits of BO. bits<3> CR; @@ -409,16 +414,16 @@ class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, - dag OL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XLForm_2<opcode, xo, lk, OL, asmstr, itin, pattern> { + dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> + : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { let BO = bo; let BI = bi; let BH = 0; } -class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<3> BF; bits<3> BFA; @@ -432,9 +437,9 @@ class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr, } // 1.7.8 XFX-Form -class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> RT; bits<10> SPR; @@ -454,14 +459,14 @@ class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, } class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, - dag OL, string asmstr, InstrItinClass itin> - : XFXForm_1<opcode, xo, OL, asmstr, itin> { + dag OOL, dag IOL, string asmstr, InstrItinClass itin> + : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { let SPR = spr; } -class XFXForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> RT; let Inst{6-10} = RT; @@ -470,9 +475,9 @@ class XFXForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } -class XFXForm_5<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<8> FXM; bits<5> ST; @@ -484,9 +489,9 @@ class XFXForm_5<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } -class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> ST; bits<8> FXM; @@ -498,20 +503,20 @@ class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } -class XFXForm_7<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : XFXForm_1<opcode, xo, OL, asmstr, itin>; + : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, - dag OL, string asmstr, InstrItinClass itin> - : XFXForm_7<opcode, xo, OL, asmstr, itin> { + dag OOL, dag IOL, string asmstr, InstrItinClass itin> + : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { let SPR = spr; } // 1.7.10 XS-Form - SRADI. -class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr, +class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> A; bits<5> RS; bits<6> SH; @@ -528,9 +533,9 @@ class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr, } // 1.7.11 XO-Form -class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OL, string asmstr, +class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> RT; bits<5> RA; bits<5> RB; @@ -548,15 +553,15 @@ class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OL, string asmstr, } class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, - dag OL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XOForm_1<opcode, xo, oe, OL, asmstr, itin, pattern> { + dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> + : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { let RB = 0; } // 1.7.12 A-Form -class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr, +class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> FRT; bits<5> FRA; bits<5> FRC; @@ -574,22 +579,22 @@ class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr, let Inst{31} = RC; } -class AForm_2<bits<6> opcode, bits<5> xo, dag OL, string asmstr, +class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : AForm_1<opcode, xo, OL, asmstr, itin, pattern> { + : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { let FRC = 0; } -class AForm_3<bits<6> opcode, bits<5> xo, dag OL, string asmstr, +class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : AForm_1<opcode, xo, OL, asmstr, itin, pattern> { + : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { let FRB = 0; } // 1.7.13 M-Form -class MForm_1<bits<6> opcode, dag OL, string asmstr, +class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> RA; bits<5> RS; bits<5> RB; @@ -608,15 +613,15 @@ class MForm_1<bits<6> opcode, dag OL, string asmstr, let Inst{31} = RC; } -class MForm_2<bits<6> opcode, dag OL, string asmstr, +class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : MForm_1<opcode, OL, asmstr, itin, pattern> { + : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { } // 1.7.14 MD-Form -class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr, +class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> RA; bits<5> RS; bits<6> SH; @@ -640,9 +645,9 @@ class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr, // E-1 VA-Form // VAForm_1 - DACB ordering. -class VAForm_1<bits<6> xo, dag OL, string asmstr, +class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; bits<5> VA; bits<5> VC; @@ -658,9 +663,9 @@ class VAForm_1<bits<6> xo, dag OL, string asmstr, } // VAForm_1a - DABC ordering. -class VAForm_1a<bits<6> xo, dag OL, string asmstr, +class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; bits<5> VA; bits<5> VB; @@ -675,9 +680,9 @@ class VAForm_1a<bits<6> xo, dag OL, string asmstr, let Inst{26-31} = xo; } -class VAForm_2<bits<6> xo, dag OL, string asmstr, +class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; bits<5> VA; bits<5> VB; @@ -694,9 +699,9 @@ class VAForm_2<bits<6> xo, dag OL, string asmstr, } // E-2 VX-Form -class VXForm_1<bits<11> xo, dag OL, string asmstr, +class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; bits<5> VA; bits<5> VB; @@ -709,17 +714,17 @@ class VXForm_1<bits<11> xo, dag OL, string asmstr, let Inst{21-31} = xo; } -class VXForm_setzero<bits<11> xo, dag OL, string asmstr, +class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : VXForm_1<xo, OL, asmstr, itin, pattern> { + : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { let VA = VD; let VB = VD; } -class VXForm_2<bits<11> xo, dag OL, string asmstr, +class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; bits<5> VB; @@ -731,9 +736,9 @@ class VXForm_2<bits<11> xo, dag OL, string asmstr, let Inst{21-31} = xo; } -class VXForm_3<bits<11> xo, dag OL, string asmstr, +class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; bits<5> IMM; @@ -746,9 +751,9 @@ class VXForm_3<bits<11> xo, dag OL, string asmstr, } /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. -class VXForm_4<bits<11> xo, dag OL, string asmstr, +class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; let Pattern = pattern; @@ -760,9 +765,9 @@ class VXForm_4<bits<11> xo, dag OL, string asmstr, } /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. -class VXForm_5<bits<11> xo, dag OL, string asmstr, +class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VB; let Pattern = pattern; @@ -774,9 +779,9 @@ class VXForm_5<bits<11> xo, dag OL, string asmstr, } // E-4 VXR-Form -class VXRForm_1<bits<10> xo, dag OL, string asmstr, +class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; bits<5> VA; bits<5> VB; @@ -792,8 +797,8 @@ class VXRForm_1<bits<10> xo, dag OL, string asmstr, } //===----------------------------------------------------------------------===// -class Pseudo<dag OL, string asmstr, list<dag> pattern> - : I<0, OL, asmstr, NoItinerary> { +class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> + : I<0, OOL, IOL, asmstr, NoItinerary> { let PPC64 = 0; let Pattern = pattern; let Inst{31-0} = 0; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index fe18978..499f537 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -297,69 +297,72 @@ def FPContractions : Predicate<"!NoExcessFPPrecision">; // Pseudo-instructions: let hasCtrlDep = 1 in { -def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), +def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "${:comment} ADJCALLSTACKDOWN", [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>; -def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), +def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt), "${:comment} ADJCALLSTACKUP", [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>; -def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS), +def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), "UPDATE_VRSAVE $rD, $rS", []>; } -def DYNALLOC : Pseudo<(ops GPRC:$result, GPRC:$negsize, memri:$fpsi), +def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "${:comment} DYNALLOC $result, $negsize, $fpsi", [(set GPRC:$result, (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>, Imp<[R1],[R1]>; -def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD),"${:comment}IMPLICIT_DEF_GPRC $rD", +def IMPLICIT_DEF_GPRC: Pseudo<(outs GPRC:$rD), (ins), + "${:comment}IMPLICIT_DEF_GPRC $rD", [(set GPRC:$rD, (undef))]>; -def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "${:comment} IMPLICIT_DEF_F8 $rD", +def IMPLICIT_DEF_F8 : Pseudo<(outs F8RC:$rD), (ins), + "${:comment} IMPLICIT_DEF_F8 $rD", [(set F8RC:$rD, (undef))]>; -def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "${:comment} IMPLICIT_DEF_F4 $rD", +def IMPLICIT_DEF_F4 : Pseudo<(outs F4RC:$rD), (ins), + "${:comment} IMPLICIT_DEF_F4 $rD", [(set F4RC:$rD, (undef))]>; // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the // scheduler into a branch sequence. let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler. PPC970_Single = 1 in { - def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F, + def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F, i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", []>; - def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F, + def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F, i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", []>; - def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F, + def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F, i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", []>; - def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F, + def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F, i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", []>; - def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F, + def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F, i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", []>; } let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in { let isReturn = 1 in - def BLR : XLForm_2_br<19, 16, 0, (ops pred:$p), + def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), "b${p:cc}lr ${p:reg}", BrB, [(retflag)]>; - def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>; + def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; } let Defs = [LR] in - def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>, + def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>, PPC970_Unit_BRU; let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1, PPC970_Unit = 7 in { let isBarrier = 1 in { - def B : IForm<18, 0, 0, (ops target:$dst), + def B : IForm<18, 0, 0, (outs), (ins target:$dst), "b $dst", BrB, [(br bb:$dst)]>; } @@ -367,7 +370,7 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, // BCC represents an arbitrary conditional branch on a predicate. // FIXME: should be able to write a pattern for PPCcondbranch, but can't use // a two-value operand where a dag node expects two operands. :( - def BCC : BForm<16, 0, 0, (ops pred:$cond, target:$dst), + def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst), "b${cond:cc} ${cond:reg}, $dst" /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; } @@ -382,13 +385,13 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7, CR0,CR1,CR5,CR6,CR7] in { // Convenient aliases for call instructions def BL_Macho : IForm<18, 0, 1, - (ops calltarget:$func, variable_ops), + (outs), (ins calltarget:$func, variable_ops), "bl $func", BrB, []>; // See Pat patterns below. def BLA_Macho : IForm<18, 1, 1, - (ops aaddr:$func, variable_ops), + (outs), (ins aaddr:$func, variable_ops), "bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>; def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1, - (ops variable_ops), + (outs), (ins variable_ops), "bctrl", BrB, [(PPCbctrl_Macho)]>; } @@ -403,41 +406,41 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7, CR0,CR1,CR5,CR6,CR7] in { // Convenient aliases for call instructions def BL_ELF : IForm<18, 0, 1, - (ops calltarget:$func, variable_ops), + (outs), (ins calltarget:$func, variable_ops), "bl $func", BrB, []>; // See Pat patterns below. def BLA_ELF : IForm<18, 1, 1, - (ops aaddr:$func, variable_ops), + (outs), (ins aaddr:$func, variable_ops), "bla $func", BrB, [(PPCcall_ELF (i32 imm:$func))]>; def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1, - (ops variable_ops), + (outs), (ins variable_ops), "bctrl", BrB, [(PPCbctrl_ELF)]>; } // DCB* instructions. -def DCBA : DCB_Form<758, 0, (ops memrr:$dst), +def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBF : DCB_Form<86, 0, (ops memrr:$dst), +def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBI : DCB_Form<470, 0, (ops memrr:$dst), +def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBST : DCB_Form<54, 0, (ops memrr:$dst), +def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBT : DCB_Form<278, 0, (ops memrr:$dst), +def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBTST : DCB_Form<246, 0, (ops memrr:$dst), +def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst), +def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst), +def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, PPC970_DGroup_Single; @@ -447,55 +450,55 @@ def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst), // Unindexed (r+i) Loads. let isLoad = 1, PPC970_Unit = 2 in { -def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src), +def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), "lbz $rD, $src", LdStGeneral, [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; -def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src), +def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src), "lha $rD, $src", LdStLHA, [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, PPC970_DGroup_Cracked; -def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src), +def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src), "lhz $rD, $src", LdStGeneral, [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; -def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src), +def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src), "lwz $rD, $src", LdStGeneral, [(set GPRC:$rD, (load iaddr:$src))]>; -def LFS : DForm_1<48, (ops F4RC:$rD, memri:$src), +def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src), "lfs $rD, $src", LdStLFDU, [(set F4RC:$rD, (load iaddr:$src))]>; -def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src), +def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src), "lfd $rD, $src", LdStLFD, [(set F8RC:$rD, (load iaddr:$src))]>; // Unindexed (r+i) Loads with Update (preinc). -def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), +def LBZU : DForm_1<35, (outs GPRC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lbzu $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), +def LHAU : DForm_1<43, (outs GPRC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lhau $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), +def LHZU : DForm_1<41, (outs GPRC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lhzu $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), +def LWZU : DForm_1<33, (outs GPRC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lwzu $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$ea_result, memri:$addr), +def LFSU : DForm_1<49, (outs F4RC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lfs $rD, $addr", LdStLFDU, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$ea_result, memri:$addr), +def LFDU : DForm_1<51, (outs F8RC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lfd $rD, $addr", LdStLFD, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; @@ -504,32 +507,32 @@ def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$ea_result, memri:$addr), // Indexed (r+r) Loads. // let isLoad = 1, PPC970_Unit = 2 in { -def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src), +def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), "lbzx $rD, $src", LdStGeneral, [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; -def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src), +def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src), "lhax $rD, $src", LdStLHA, [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, PPC970_DGroup_Cracked; -def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src), +def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src), "lhzx $rD, $src", LdStGeneral, [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; -def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src), +def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src), "lwzx $rD, $src", LdStGeneral, [(set GPRC:$rD, (load xaddr:$src))]>; -def LHBRX : XForm_1<31, 790, (ops GPRC:$rD, memrr:$src), +def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src), "lhbrx $rD, $src", LdStGeneral, [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>; -def LWBRX : XForm_1<31, 534, (ops GPRC:$rD, memrr:$src), +def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src), "lwbrx $rD, $src", LdStGeneral, [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>; -def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src), +def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src), "lfsx $frD, $src", LdStLFDU, [(set F4RC:$frD, (load xaddr:$src))]>; -def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src), +def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src), "lfdx $frD, $src", LdStLFDU, [(set F8RC:$frD, (load xaddr:$src))]>; } @@ -540,52 +543,52 @@ def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src), // Unindexed (r+i) Stores. let isStore = 1, noResults = 1, PPC970_Unit = 2 in { -def STB : DForm_1<38, (ops GPRC:$rS, memri:$src), +def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src), "stb $rS, $src", LdStGeneral, [(truncstorei8 GPRC:$rS, iaddr:$src)]>; -def STH : DForm_1<44, (ops GPRC:$rS, memri:$src), +def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src), "sth $rS, $src", LdStGeneral, [(truncstorei16 GPRC:$rS, iaddr:$src)]>; -def STW : DForm_1<36, (ops GPRC:$rS, memri:$src), +def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src), "stw $rS, $src", LdStGeneral, [(store GPRC:$rS, iaddr:$src)]>; -def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst), +def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst), "stfs $rS, $dst", LdStUX, [(store F4RC:$rS, iaddr:$dst)]>; -def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst), +def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst), "stfd $rS, $dst", LdStUX, [(store F8RC:$rS, iaddr:$dst)]>; } // Unindexed (r+i) Stores with Update (preinc). let isStore = 1, PPC970_Unit = 2 in { -def STBU : DForm_1<39, (ops ptr_rc:$ea_res, GPRC:$rS, +def STBU : DForm_1<39, (outs), (ins ptr_rc:$ea_res, GPRC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "stbu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff))]>, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; -def STHU : DForm_1<45, (ops ptr_rc:$ea_res, GPRC:$rS, +def STHU : DForm_1<45, (outs), (ins ptr_rc:$ea_res, GPRC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "sthu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff))]>, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; -def STWU : DForm_1<37, (ops ptr_rc:$ea_res, GPRC:$rS, +def STWU : DForm_1<37, (outs), (ins ptr_rc:$ea_res, GPRC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "stwu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff))]>, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; -def STFSU : DForm_1<37, (ops ptr_rc:$ea_res, F4RC:$rS, +def STFSU : DForm_1<37, (outs), (ins ptr_rc:$ea_res, F4RC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "stfsu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff))]>, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; -def STFDU : DForm_1<37, (ops ptr_rc:$ea_res, F8RC:$rS, +def STFDU : DForm_1<37, (outs), (ins ptr_rc:$ea_res, F8RC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "stfdu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg, @@ -597,37 +600,37 @@ def STFDU : DForm_1<37, (ops ptr_rc:$ea_res, F8RC:$rS, // Indexed (r+r) Stores. // let isStore = 1, noResults = 1, PPC970_Unit = 2 in { -def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst), +def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst), "stbx $rS, $dst", LdStGeneral, [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, PPC970_DGroup_Cracked; -def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst), +def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst), "sthx $rS, $dst", LdStGeneral, [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, PPC970_DGroup_Cracked; -def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst), +def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst), "stwx $rS, $dst", LdStGeneral, [(store GPRC:$rS, xaddr:$dst)]>, PPC970_DGroup_Cracked; -def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), +def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB), "stwux $rS, $rA, $rB", LdStGeneral, []>; -def STHBRX: XForm_8<31, 918, (ops GPRC:$rS, memrr:$dst), +def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst), "sthbrx $rS, $dst", LdStGeneral, [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>, PPC970_DGroup_Cracked; -def STWBRX: XForm_8<31, 662, (ops GPRC:$rS, memrr:$dst), +def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst), "stwbrx $rS, $dst", LdStGeneral, [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>, PPC970_DGroup_Cracked; -def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst), +def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst), "stfiwx $frS, $dst", LdStUX, [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; -def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst), +def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst), "stfsx $frS, $dst", LdStUX, [(store F4RC:$frS, xaddr:$dst)]>; -def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst), +def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst), "stfdx $frS, $dst", LdStUX, [(store F8RC:$frS, xaddr:$dst)]>; } @@ -638,140 +641,140 @@ def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst), // let PPC970_Unit = 1 in { // FXU Operations. -def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), +def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "addi $rD, $rA, $imm", IntGeneral, [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; -def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), +def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "addic $rD, $rA, $imm", IntGeneral, [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, PPC970_DGroup_Cracked; -def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), +def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "addic. $rD, $rA, $imm", IntGeneral, []>; -def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm), +def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm), "addis $rD, $rA, $imm", IntGeneral, [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>; -def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym), +def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym), "la $rD, $sym($rA)", IntGeneral, [(set GPRC:$rD, (add GPRC:$rA, (PPClo tglobaladdr:$sym, 0)))]>; -def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), +def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "mulli $rD, $rA, $imm", IntMulLI, [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; -def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), +def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "subfic $rD, $rA, $imm", IntGeneral, [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; -def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm), +def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), "li $rD, $imm", IntGeneral, [(set GPRC:$rD, immSExt16:$imm)]>; -def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm), +def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), "lis $rD, $imm", IntGeneral, [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; } let PPC970_Unit = 1 in { // FXU Operations. -def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), +def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), "andi. $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, isDOT; -def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), +def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), "andis. $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, isDOT; -def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), +def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), "ori $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; -def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), +def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), "oris $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; -def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), +def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), "xori $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; -def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), +def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), "xoris $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; -def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral, +def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral, []>; -def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), +def CMPWI : DForm_5_ext<11, (outs), (ins CRRC:$crD, GPRC:$rA, s16imm:$imm), "cmpwi $crD, $rA, $imm", IntCompare>; -def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), +def CMPLWI : DForm_6_ext<10, (outs), (ins CRRC:$dst, GPRC:$src1, u16imm:$src2), "cmplwi $dst, $src1, $src2", IntCompare>; } let PPC970_Unit = 1 in { // FXU Operations. -def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "nand $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; -def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "and $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; -def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "andc $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; -def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "or $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; -def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "nor $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; -def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "orc $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; -def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "eqv $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; -def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "xor $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; -def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "slw $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; -def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "srw $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; -def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "sraw $rA, $rS, $rB", IntShift, [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; } let PPC970_Unit = 1 in { // FXU Operations. -def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), +def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH), "srawi $rA, $rS, $SH", IntShift, [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; -def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS), +def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS), "cntlzw $rA, $rS", IntGeneral, [(set GPRC:$rA, (ctlz GPRC:$rS))]>; -def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS), +def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS), "extsb $rA, $rS", IntGeneral, [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; -def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS), +def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS), "extsh $rA, $rS", IntGeneral, [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; -def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), +def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), "cmpw $crD, $rA, $rB", IntCompare>; -def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), +def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), "cmplw $crD, $rA, $rB", IntCompare>; } let PPC970_Unit = 3 in { // FPU Operations. -//def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB), +//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), // "fcmpo $crD, $fA, $fB", FPCompare>; -def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB), +def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB), "fcmpu $crD, $fA, $fB", FPCompare>; -def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB), +def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB), "fcmpu $crD, $fA, $fB", FPCompare>; -def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB), +def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB), "fctiwz $frD, $frB", FPGeneral, [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; -def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB), +def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB), "frsp $frD, $frB", FPGeneral, [(set F4RC:$frD, (fround F8RC:$frB))]>; -def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB), +def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB), "fsqrt $frD, $frB", FPSqrt, [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; -def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB), +def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB), "fsqrts $frD, $frB", FPSqrt, [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; } @@ -782,37 +785,37 @@ def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB), /// often coalesced away and we don't want the dispatch group builder to think /// that they will fill slots (which could cause the load of a LSU reject to /// sneak into a d-group with a store). -def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB), +def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB), "fmr $frD, $frB", FPGeneral, []>, // (set F4RC:$frD, F4RC:$frB) PPC970_Unit_Pseudo; -def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB), +def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB), "fmr $frD, $frB", FPGeneral, []>, // (set F8RC:$frD, F8RC:$frB) PPC970_Unit_Pseudo; -def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB), +def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB), "fmr $frD, $frB", FPGeneral, [(set F8RC:$frD, (fextend F4RC:$frB))]>, PPC970_Unit_Pseudo; let PPC970_Unit = 3 in { // FPU Operations. // These are artificially split into two different forms, for 4/8 byte FP. -def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB), +def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB), "fabs $frD, $frB", FPGeneral, [(set F4RC:$frD, (fabs F4RC:$frB))]>; -def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB), +def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB), "fabs $frD, $frB", FPGeneral, [(set F8RC:$frD, (fabs F8RC:$frB))]>; -def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB), +def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB), "fnabs $frD, $frB", FPGeneral, [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; -def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB), +def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB), "fnabs $frD, $frB", FPGeneral, [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; -def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB), +def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB), "fneg $frD, $frB", FPGeneral, [(set F4RC:$frD, (fneg F4RC:$frB))]>; -def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB), +def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB), "fneg $frD, $frB", FPGeneral, [(set F8RC:$frD, (fneg F8RC:$frB))]>; } @@ -820,48 +823,52 @@ def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB), // XL-Form instructions. condition register logical ops. // -def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA), +def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA), "mcrf $BF, $BFA", BrMCR>, PPC970_DGroup_First, PPC970_Unit_CRU; -def CREQV : XLForm_1<19, 289, (ops CRRC:$CRD, CRRC:$CRA, CRRC:$CRB), +def CREQV : XLForm_1<19, 289, (outs CRRC:$CRD), (ins CRRC:$CRA, CRRC:$CRB), "creqv $CRD, $CRA, $CRB", BrCR, []>; -def SETCR : XLForm_1_ext<19, 289, (ops CRRC:$dst), +def SETCR : XLForm_1_ext<19, 289, (outs CRRC:$dst), (ins), "creqv $dst, $dst, $dst", BrCR, []>; // XFX-Form instructions. Instructions that deal with SPRs. // -def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>, +def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins), + "mfctr $rT", SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; let Pattern = [(PPCmtctr GPRC:$rS)] in { -def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>, +def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS), + "mtctr $rS", SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } -def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>, +def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS), + "mtlr $rS", SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; -def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>, +def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins), + "mflr $rT", SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like // a GPR on the PPC970. As such, copies in and out have the same performance // characteristics as an OR instruction. -def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), +def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS), "mtspr 256, $rS", IntGeneral>, PPC970_DGroup_Single, PPC970_Unit_FXU; -def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), +def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins), "mfspr $rT, 256", IntGeneral>, PPC970_DGroup_First, PPC970_Unit_FXU; -def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS), +def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS), "mtcrf $FXM, $rS", BrMCRX>, PPC970_MicroCode, PPC970_Unit_CRU; -def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>, +def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>, PPC970_MicroCode, PPC970_Unit_CRU; -def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM), +def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), "mfcr $rT, $FXM", SprMFCR>, PPC970_DGroup_First, PPC970_Unit_CRU; @@ -869,56 +876,56 @@ let PPC970_Unit = 1 in { // FXU Operations. // XO-Form instructions. Arithmetic instructions that can set overflow bit // -def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "add $rT, $rA, $rB", IntGeneral, [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; -def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "addc $rT, $rA, $rB", IntGeneral, [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, PPC970_DGroup_Cracked; -def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "adde $rT, $rA, $rB", IntGeneral, [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; -def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "divw $rT, $rA, $rB", IntDivW, [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, PPC970_DGroup_First, PPC970_DGroup_Cracked; -def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "divwu $rT, $rA, $rB", IntDivW, [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, PPC970_DGroup_First, PPC970_DGroup_Cracked; -def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "mulhw $rT, $rA, $rB", IntMulHW, [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; -def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "mulhwu $rT, $rA, $rB", IntMulHWU, [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; -def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "mullw $rT, $rA, $rB", IntMulHW, [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; -def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "subf $rT, $rA, $rB", IntGeneral, [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; -def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "subfc $rT, $rA, $rB", IntGeneral, [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, PPC970_DGroup_Cracked; -def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "subfe $rT, $rA, $rB", IntGeneral, [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; -def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA), +def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA), "addme $rT, $rA", IntGeneral, [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>; -def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA), +def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA), "addze $rT, $rA", IntGeneral, [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; -def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA), +def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA), "neg $rT, $rA", IntGeneral, [(set GPRC:$rT, (ineg GPRC:$rA))]>; -def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA), +def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA), "subfme $rT, $rA", IntGeneral, [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>; -def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA), +def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA), "subfze $rT, $rA", IntGeneral, [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; } @@ -928,49 +935,49 @@ def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA), // let PPC970_Unit = 3 in { // FPU Operations. def FMADD : AForm_1<63, 29, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), F8RC:$FRB))]>, Requires<[FPContractions]>; def FMADDS : AForm_1<59, 29, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), F4RC:$FRB))]>, Requires<[FPContractions]>; def FMSUB : AForm_1<63, 28, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), F8RC:$FRB))]>, Requires<[FPContractions]>; def FMSUBS : AForm_1<59, 28, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), F4RC:$FRB))]>, Requires<[FPContractions]>; def FNMADD : AForm_1<63, 31, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), F8RC:$FRB)))]>, Requires<[FPContractions]>; def FNMADDS : AForm_1<59, 31, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), F4RC:$FRB)))]>, Requires<[FPContractions]>; def FNMSUB : AForm_1<63, 30, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), F8RC:$FRB)))]>, Requires<[FPContractions]>; def FNMSUBS : AForm_1<59, 30, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), F4RC:$FRB)))]>, @@ -980,43 +987,43 @@ def FNMSUBS : AForm_1<59, 30, // should use an FMRSD if the input comparison value really wants to be a float) // and 4/8 byte forms for the result and operand type.. def FSELD : AForm_1<63, 23, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; def FSELS : AForm_1<63, 23, - (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), + (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; def FADD : AForm_2<63, 21, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), "fadd $FRT, $FRA, $FRB", FPGeneral, [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; def FADDS : AForm_2<59, 21, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), "fadds $FRT, $FRA, $FRB", FPGeneral, [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; def FDIV : AForm_2<63, 18, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), "fdiv $FRT, $FRA, $FRB", FPDivD, [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; def FDIVS : AForm_2<59, 18, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), "fdivs $FRT, $FRA, $FRB", FPDivS, [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; def FMUL : AForm_3<63, 25, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), "fmul $FRT, $FRA, $FRB", FPFused, [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; def FMULS : AForm_3<59, 25, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), "fmuls $FRT, $FRA, $FRB", FPGeneral, [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; def FSUB : AForm_2<63, 20, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), "fsub $FRT, $FRA, $FRB", FPGeneral, [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; def FSUBS : AForm_2<59, 20, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), "fsubs $FRT, $FRA, $FRB", FPGeneral, [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; } @@ -1027,21 +1034,21 @@ let PPC970_Unit = 1 in { // FXU Operations. let isCommutable = 1 in { // RLWIMI can be commuted if the rotate amount is zero. def RLWIMI : MForm_2<20, - (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, + (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; } def RLWINM : MForm_2<21, - (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), + (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, []>; def RLWINMo : MForm_2<21, - (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), + (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, []>, isDOT, PPC970_DGroup_Cracked; def RLWNM : MForm_2<23, - (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), + (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, []>; } @@ -1051,7 +1058,7 @@ def RLWNM : MForm_2<23, // DWARF Pseudo Instructions // -def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file), +def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), "${:comment} .loc $file, $line, $col", [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>; diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 19780a8..ee320f8 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -248,8 +248,8 @@ void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB, MBB.insert(I, MI); } -const unsigned* PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) - const { +const unsigned* +PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { // 32-bit Darwin calling convention. static const unsigned Macho32_CalleeSavedRegs[] = { PPC::R13, PPC::R14, PPC::R15, diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index 4112034..0a1446e 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -59,8 +59,8 @@ public: const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; - const TargetRegisterClass* const* getCalleeSavedRegClasses( - const MachineFunction *MF = 0) const; + const TargetRegisterClass* const* + getCalleeSavedRegClasses(const MachineFunction *MF = 0) const; BitVector getReservedRegs(const MachineFunction &MF) const; |