Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28889 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 28 insertions, 28 deletions

diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 6d78a5d..108f03d 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -465,7 +465,7 @@ void PPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
       O << ", " << (unsigned int)SH << "\n";
       return;
     }
-  } else if (MI->getOpcode() == PPC::OR4 || MI->getOpcode() == PPC::OR8) {
+  } else if (MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) {
     if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
       O << "mr ";
       printOperand(MI, 0);
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index 3545e2b..09e8f9f 100644
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -22,7 +22,29 @@ def symbolLo64 : Operand<i64> {
   let PrintMethod = "printSymbolLo";
 }
 
+//===----------------------------------------------------------------------===//
+// 64-bit transformation functions.
+//
+
+def SHL64 : SDNodeXForm<imm, [{
+  // Transformation function: 63 - imm
+  return getI32Imm(63 - N->getValue());
+}]>;
 
+def SRL64 : SDNodeXForm<imm, [{
+  // Transformation function: 64 - imm
+  return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
+}]>;
+
+def HI32_48 : SDNodeXForm<imm, [{
+  // Transformation function: shift the immediate value down into the low bits.
+  return getI32Imm((unsigned short)(N->getValue() >> 32));
+}]>;
+
+def HI48_64 : SDNodeXForm<imm, [{
+  // Transformation function: shift the immediate value down into the low bits.
+  return getI32Imm((unsigned short)(N->getValue() >> 48));
+}]>;
 
 
 //===----------------------------------------------------------------------===//
@@ -238,17 +260,6 @@ def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
 // Instruction Patterns
 //
 
-def HI32_48 : SDNodeXForm<imm, [{
-  // Transformation function: shift the immediate value down into the low bits.
-  return getI32Imm((unsigned short)(N->getValue() >> 32));
-}]>;
-
-def HI48_64 : SDNodeXForm<imm, [{
-  // Transformation function: shift the immediate value down into the low bits.
-  return getI32Imm((unsigned short)(N->getValue() >> 48));
-}]>;
-
-
 // Immediate support.
 // Handled above:
 //   sext(0x0000_0000_0000_FFFF,  i8) -> li imm
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index 9ed4393..87e9127 100644
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -785,7 +785,6 @@ class VXRForm_1<bits<10> xo, dag OL, string asmstr,
 class Pseudo<dag OL, string asmstr, list<dag> pattern>
     : I<0, OL, asmstr, NoItinerary> {
   let PPC64 = 0;
-  let VMX = 0;
   let Pattern = pattern;
   let Inst{31-0} = 0;
 }
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 9390442..a2ba4fe 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -35,7 +35,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
                                unsigned& sourceReg,
                                unsigned& destReg) const {
   MachineOpCode oc = MI.getOpcode();
-  if (oc == PPC::OR4 || oc == PPC::OR8 || oc == PPC::VOR ||
+  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
       oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
     assert(MI.getNumOperands() == 3 &&
            MI.getOperand(0).isRegister() &&
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 341c47a..aeb0142 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -97,21 +97,11 @@ def SHL32 : SDNodeXForm<imm, [{
   return getI32Imm(31 - N->getValue());
 }]>;
 
-def SHL64 : SDNodeXForm<imm, [{
-  // Transformation function: 63 - imm
-  return getI32Imm(63 - N->getValue());
-}]>;
-
 def SRL32 : SDNodeXForm<imm, [{
   // Transformation function: 32 - imm
   return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
 }]>;
 
-def SRL64 : SDNodeXForm<imm, [{
-  // Transformation function: 64 - imm
-  return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
-}]>;
-
 def LO16 : SDNodeXForm<imm, [{
   // Transformation function: get the low 16 bits.
   return getI32Imm((unsigned short)N->getValue());
@@ -485,7 +475,7 @@ def AND  : XForm_6<31,  28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
 def ANDC : XForm_6<31,  60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "andc $rA, $rS, $rB", IntGeneral,
                    [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
-def OR4  : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def OR   : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "or $rA, $rS, $rB", IntGeneral,
                    [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
 def NOR  : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 8cc2da5..41e95a3 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -189,7 +189,7 @@ void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
                                    unsigned DestReg, unsigned SrcReg,
                                    const TargetRegisterClass *RC) const {
   if (RC == PPC::GPRCRegisterClass) {
-    BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+    BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
   } else if (RC == PPC::G8RCRegisterClass) {
     BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
   } else if (RC == PPC::F4RCRegisterClass) {
@@ -282,7 +282,7 @@ MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
   // it takes more than one instruction to store it.
   unsigned Opc = MI->getOpcode();
   
-  if ((Opc == PPC::OR4 &&
+  if ((Opc == PPC::OR &&
        MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
     if (OpNum == 0) {  // move -> store
       unsigned InReg = MI->getOperand(1).getReg();
@@ -631,7 +631,7 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
   if (HasFP) {
     BuildMI(MBB, MBBI, PPC::STW, 3)
       .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1);
-    BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
+    BuildMI(MBB, MBBI, PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
   }
 }