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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-26 01:21:14 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-26 01:21:14 +0000 |
commit | b555609e73f5091bf8180c0875fb1fa6c5ad0e7a (patch) | |
tree | 96d997b82dbd5e9fa80e40dd406b0e55db187b2d /lib/Target/PowerPC | |
parent | a4e4ffd389497eb28f5fe91521fb71da4340e5d6 (diff) | |
download | external_llvm-b555609e73f5091bf8180c0875fb1fa6c5ad0e7a.zip external_llvm-b555609e73f5091bf8180c0875fb1fa6c5ad0e7a.tar.gz external_llvm-b555609e73f5091bf8180c0875fb1fa6c5ad0e7a.tar.bz2 |
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC')
-rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.td | 30 |
1 files changed, 19 insertions, 11 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 8604f54..5aa6e02 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -10,15 +10,6 @@ // //===----------------------------------------------------------------------===// -let Namespace = "PPC" in { -def sub_lt : SubRegIndex; -def sub_gt : SubRegIndex; -def sub_eq : SubRegIndex; -def sub_un : SubRegIndex; -def sub_32 : SubRegIndex; -} - - class PPCReg<string n> : Register<n> { let Namespace = "PPC"; } @@ -34,7 +25,6 @@ class GPR<bits<5> num, string n> : PPCReg<n> { class GP8<GPR SubReg, string n> : PPCReg<n> { field bits<5> Num = SubReg.Num; let SubRegs = [SubReg]; - let SubRegIndices = [sub_32]; } // SPR - One of the 32-bit special-purpose registers @@ -235,7 +225,6 @@ def CR7EQ : CRBIT<30, "30">, DwarfRegNum<[0]>; def CR7UN : CRBIT<31, "31">, DwarfRegNum<[0]>; // Condition registers -let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in { def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68]>; def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69]>; def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70]>; @@ -244,8 +233,27 @@ def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72]>; def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73]>; def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74]>; def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75]>; + +let Namespace = "PPC" in { +def sub_lt : SubRegIndex; +def sub_gt : SubRegIndex; +def sub_eq : SubRegIndex; +def sub_un : SubRegIndex; } +def : SubRegSet<sub_lt, + [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], + [CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT]>; +def : SubRegSet<sub_gt, + [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], + [CR0GT, CR1GT, CR2GT, CR3GT, CR4GT, CR5GT, CR6GT, CR7GT]>; +def : SubRegSet<sub_eq, + [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], + [CR0EQ, CR1EQ, CR2EQ, CR3EQ, CR4EQ, CR5EQ, CR6EQ, CR7EQ]>; +def : SubRegSet<sub_un, + [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], + [CR0UN, CR1UN, CR2UN, CR3UN, CR4UN, CR5UN, CR6UN, CR7UN]>; + // Link register def LR : SPR<8, "lr">, DwarfRegNum<[65]>; //let Aliases = [LR] in |