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| author | Evan Cheng <evan.cheng@apple.com> | 2010-02-02 21:29:10 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-02-02 21:29:10 +0000 |
| commit | ca6c93430e98e3fb0eaf40aa543ea1dc45cf35d7 (patch) | |
| tree | eb971fa329023daf285f142fe0d7e5805b1424e5 /lib/Target/PowerPC | |
| parent | cd8ca7e941dfe24aa8b61d3fda092d4b0e224502 (diff) | |
| download | external_llvm-ca6c93430e98e3fb0eaf40aa543ea1dc45cf35d7.zip external_llvm-ca6c93430e98e3fb0eaf40aa543ea1dc45cf35d7.tar.gz external_llvm-ca6c93430e98e3fb0eaf40aa543ea1dc45cf35d7.tar.bz2 | |
Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95130 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 2a4fb02..310ace8 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2674,7 +2674,7 @@ PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, } SDValue -PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, +PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index 9c390ac..4bf70b8 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -430,7 +430,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, + LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, |