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author | Chris Lattner <sabre@nondot.org> | 2007-12-08 07:04:58 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2007-12-08 07:04:58 +0000 |
commit | d96428597b9a4bcf3c0702bbb497796b922c2e91 (patch) | |
tree | f1a1798418a3653d79be07231d09b8a63f4078bd /lib/Target/PowerPC | |
parent | 3fc027df4fca0355717515abb4d6e3753e6dee2a (diff) | |
download | external_llvm-d96428597b9a4bcf3c0702bbb497796b922c2e91.zip external_llvm-d96428597b9a4bcf3c0702bbb497796b922c2e91.tar.gz external_llvm-d96428597b9a4bcf3c0702bbb497796b922c2e91.tar.bz2 |
Fix a significant code quality regression I introduced on PPC64 quite
a while ago. We now produce:
_foo:
mflr r0
std r0, 16(r1)
ld r2, 16(r1)
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr
instead of:
_foo:
mflr r0
std r0, 16(r1)
lis r0, 0
ori r0, r0, 16
ldx r2, r1, r0
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr
for:
void foo(void **X) {
*X = __builtin_return_address(0);
}
on ppc64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44701 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC')
-rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index c574f70..150bda7 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -817,7 +817,7 @@ void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // clear can be encoded. This is extremely uncommon, because normally you // only "std" to a stack slot that is at least 4-byte aligned, but it can // happen in invalid code. - if (isInt16(Offset) && (!isIXAddr || (isIXAddr & 3) == 0)) { + if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) { if (isIXAddr) Offset >>= 2; // The actual encoded value has the low two bits zero. MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); |