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| author | Chris Lattner <sabre@nondot.org> | 2006-01-31 19:20:21 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-01-31 19:20:21 +0000 |
| commit | ddc787dfdc75fb2d78eb3e5793ca0f417ad74fd3 (patch) | |
| tree | c8149eeeaf4a4253366e18ad4f1165cc4af17421 /lib/Target/PowerPC | |
| parent | 59ad781e0118021d1ca7dfbc9f8db2ed828745e0 (diff) | |
| download | external_llvm-ddc787dfdc75fb2d78eb3e5793ca0f417ad74fd3.zip external_llvm-ddc787dfdc75fb2d78eb3e5793ca0f417ad74fd3.tar.gz external_llvm-ddc787dfdc75fb2d78eb3e5793ca0f417ad74fd3.tar.bz2 | |
add info about the inline asm register constraints for PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25853 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 56 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.h | 4 |
2 files changed, 60 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index c4f6be8..8b5546d 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -20,6 +20,7 @@ #include "llvm/CodeGen/SSARegMap.h" #include "llvm/Constants.h" #include "llvm/Function.h" +#include "llvm/ADT/VectorExtras.h" using namespace llvm; PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) @@ -951,3 +952,58 @@ PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, return BB; } +std::vector<unsigned> PPCTargetLowering:: +getRegForInlineAsmConstraint(const std::string &Constraint) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { // GCC RS6000 Constraint Letters + default: break; // Unknown constriant letter + case 'b': + return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 , + PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 , + PPC::R8 , PPC::R9 , PPC::R10, PPC::R11, + PPC::R12, PPC::R13, PPC::R14, PPC::R15, + PPC::R16, PPC::R17, PPC::R18, PPC::R19, + PPC::R20, PPC::R21, PPC::R22, PPC::R23, + PPC::R24, PPC::R25, PPC::R26, PPC::R27, + PPC::R28, PPC::R29, PPC::R30, PPC::R31, + 0); + case 'r': + return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 , + PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 , + PPC::R8 , PPC::R9 , PPC::R10, PPC::R11, + PPC::R12, PPC::R13, PPC::R14, PPC::R15, + PPC::R16, PPC::R17, PPC::R18, PPC::R19, + PPC::R20, PPC::R21, PPC::R22, PPC::R23, + PPC::R24, PPC::R25, PPC::R26, PPC::R27, + PPC::R28, PPC::R29, PPC::R30, PPC::R31, + 0); + case 'f': + return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 , + PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 , + PPC::F8 , PPC::F9 , PPC::F10, PPC::F11, + PPC::F12, PPC::F13, PPC::F14, PPC::F15, + PPC::F16, PPC::F17, PPC::F18, PPC::F19, + PPC::F20, PPC::F21, PPC::F22, PPC::F23, + PPC::F24, PPC::F25, PPC::F26, PPC::F27, + PPC::F28, PPC::F29, PPC::F30, PPC::F31, + 0); + case 'v': + return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , + PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , + PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, + PPC::V12, PPC::V13, PPC::V14, PPC::V15, + PPC::V16, PPC::V17, PPC::V18, PPC::V19, + PPC::V20, PPC::V21, PPC::V22, PPC::V23, + PPC::V24, PPC::V25, PPC::V26, PPC::V27, + PPC::V28, PPC::V29, PPC::V30, PPC::V31, + 0); + case 'y': + return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, + PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, + 0); + } + } + + // Handle explicit register names. + return TargetLowering::getRegForInlineAsmConstraint(Constraint); +} diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index 9f6b77b..30db16c 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -96,6 +96,10 @@ namespace llvm { virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, MachineBasicBlock *MBB); + + std::vector<unsigned> + getRegForInlineAsmConstraint(const std::string &Constraint) const; + }; } |