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| author | Chris Lattner <sabre@nondot.org> | 2006-06-20 23:11:59 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-06-20 23:11:59 +0000 |
| commit | f2c5bca165fa654ad46f2b232773b2116b734b63 (patch) | |
| tree | b7c313a7daa7620fb2111949ed4bb73368a1894b /lib/Target/PowerPC | |
| parent | 4b25b404860c2e4a2845adfb9d78e46c303ac328 (diff) | |
| download | external_llvm-f2c5bca165fa654ad46f2b232773b2116b734b63.zip external_llvm-f2c5bca165fa654ad46f2b232773b2116b734b63.tar.gz external_llvm-f2c5bca165fa654ad46f2b232773b2116b734b63.tar.bz2 | |
add some logical ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28887 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstr64Bit.td | 31 |
1 files changed, 28 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index b5adf95..3545e2b 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -32,9 +32,6 @@ def symbolLo64 : Operand<i64> { let PPC970_Unit = 1 in { // FXU Operations. // Copies, extends, truncates. -def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), - "or $rA, $rS, $rB", IntGeneral, - [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB), "or $rA, $rS, $rB", IntGeneral, []>; @@ -50,6 +47,32 @@ def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm), [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; // Logical ops. +def NAND8: XForm_6<31, 476, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), + "nand $rA, $rS, $rB", IntGeneral, + [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; +def AND8 : XForm_6<31, 28, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), + "and $rA, $rS, $rB", IntGeneral, + [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; +def ANDC8: XForm_6<31, 60, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), + "andc $rA, $rS, $rB", IntGeneral, + [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; +def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), + "or $rA, $rS, $rB", IntGeneral, + [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; +def NOR8 : XForm_6<31, 124, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), + "nor $rA, $rS, $rB", IntGeneral, + [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; +def ORC8 : XForm_6<31, 412, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), + "orc $rA, $rS, $rB", IntGeneral, + [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; +def EQV8 : XForm_6<31, 284, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), + "eqv $rA, $rS, $rB", IntGeneral, + [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; +def XOR8 : XForm_6<31, 316, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), + "xor $rA, $rS, $rB", IntGeneral, + [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; + +// Logical ops with immediate. def ANDIo8 : DForm_4<28, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), "andi. $dst, $src1, $src2", IntGeneral, [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, @@ -252,6 +275,8 @@ def zext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{ def : Pat<(i64 zext_0x0000_0000_FFFF_FFFF_i16:$imm), (ORIS8 (ORI8 (LI8 0), (LO16 imm:$imm)), (HI16 imm:$imm))>; +// FIXME: Handle smart forms where the top 32-bits are set. Right now, stuff +// like 0xABCD0123BCDE0000 hits the case below, which produces ORI R, R, 0's! // Fully general (and most expensive: 6 instructions!) immediate pattern. def : Pat<(i64 imm:$imm), |