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author | Stephen Hines <srhines@google.com> | 2014-04-23 16:57:46 -0700 |
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committer | Stephen Hines <srhines@google.com> | 2014-04-24 15:53:16 -0700 |
commit | 36b56886974eae4f9c5ebc96befd3e7bfe5de338 (patch) | |
tree | e6cfb69fbbd937f450eeb83bfb83b9da3b01275a /lib/Target/R600/AMDGPUAsmPrinter.cpp | |
parent | 69a8640022b04415ae9fac62f8ab090601d8f889 (diff) | |
download | external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.zip external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.gz external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.bz2 |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
Diffstat (limited to 'lib/Target/R600/AMDGPUAsmPrinter.cpp')
-rw-r--r-- | lib/Target/R600/AMDGPUAsmPrinter.cpp | 81 |
1 files changed, 57 insertions, 24 deletions
diff --git a/lib/Target/R600/AMDGPUAsmPrinter.cpp b/lib/Target/R600/AMDGPUAsmPrinter.cpp index 67bdba2..b166c45 100644 --- a/lib/Target/R600/AMDGPUAsmPrinter.cpp +++ b/lib/Target/R600/AMDGPUAsmPrinter.cpp @@ -46,28 +46,26 @@ extern "C" void LLVMInitializeR600AsmPrinter() { } AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) - : AsmPrinter(TM, Streamer) -{ - DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode() && - ! Streamer.hasRawTextSupport(); + : AsmPrinter(TM, Streamer) { + DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode(); } -/// We need to override this function so we can avoid -/// the call to EmitFunctionHeader(), which the MCPureStreamer can't handle. bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) { SetupMachineFunction(MF); - if (OutStreamer.hasRawTextSupport()) { - OutStreamer.EmitRawText("@" + MF.getName() + ":"); - } + + OutStreamer.emitRawComment(Twine('@') + MF.getName() + Twine(':')); MCContext &Context = getObjFileLowering().getContext(); const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0, SectionKind::getReadOnly()); OutStreamer.SwitchSection(ConfigSection); + const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>(); + SIProgramInfo KernelInfo; if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) { - EmitProgramInfoSI(MF); + findNumUsedRegistersSI(MF, KernelInfo.NumSGPR, KernelInfo.NumVGPR); + EmitProgramInfoSI(MF, KernelInfo); } else { EmitProgramInfoR600(MF); } @@ -79,6 +77,26 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) { OutStreamer.SwitchSection(getObjFileLowering().getTextSection()); EmitFunctionBody(); + if (isVerbose()) { + const MCSectionELF *CommentSection + = Context.getELFSection(".AMDGPU.csdata", + ELF::SHT_PROGBITS, 0, + SectionKind::getReadOnly()); + OutStreamer.SwitchSection(CommentSection); + + if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) { + OutStreamer.emitRawComment(" Kernel info:", false); + OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR), + false); + OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR), + false); + } else { + R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>(); + OutStreamer.emitRawComment( + Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize))); + } + } + if (STM.dumpCode()) { #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) MF.dump(); @@ -166,8 +184,9 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) { } } -void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF) { - const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>(); +void AMDGPUAsmPrinter::findNumUsedRegistersSI(MachineFunction &MF, + unsigned &NumSGPR, + unsigned &NumVGPR) const { unsigned MaxSGPR = 0; unsigned MaxVGPR = 0; bool VCCUsed = false; @@ -184,16 +203,15 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF) { unsigned numOperands = MI.getNumOperands(); for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) { MachineOperand &MO = MI.getOperand(op_idx); - unsigned maxUsed; unsigned width = 0; bool isSGPR = false; - unsigned reg; - unsigned hwReg; + if (!MO.isReg()) { continue; } - reg = MO.getReg(); - if (reg == AMDGPU::VCC) { + unsigned reg = MO.getReg(); + if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO || + reg == AMDGPU::VCC_HI) { VCCUsed = true; continue; } @@ -240,10 +258,10 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF) { isSGPR = false; width = 16; } else { - assert(!"Unknown register class"); + llvm_unreachable("Unknown register class"); } - hwReg = RI->getEncodingValue(reg) & 0xff; - maxUsed = hwReg + width - 1; + unsigned hwReg = RI->getEncodingValue(reg) & 0xff; + unsigned maxUsed = hwReg + width - 1; if (isSGPR) { MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR; } else { @@ -252,10 +270,24 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF) { } } } - if (VCCUsed) { + + if (VCCUsed) MaxSGPR += 2; - } - SIMachineFunctionInfo * MFI = MF.getInfo<SIMachineFunctionInfo>(); + + NumSGPR = MaxSGPR; + NumVGPR = MaxVGPR; +} + +void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &Out, + MachineFunction &MF) const { + findNumUsedRegistersSI(MF, Out.NumSGPR, Out.NumVGPR); +} + +void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF, + const SIProgramInfo &KernelInfo) { + const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>(); + + SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); unsigned RsrcReg; switch (MFI->ShaderType) { default: // Fall through @@ -266,7 +298,8 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF) { } OutStreamer.EmitIntValue(RsrcReg, 4); - OutStreamer.EmitIntValue(S_00B028_VGPRS(MaxVGPR / 4) | S_00B028_SGPRS(MaxSGPR / 8), 4); + OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.NumVGPR / 4) | + S_00B028_SGPRS(KernelInfo.NumSGPR / 8), 4); unsigned LDSAlignShift; if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) { |