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authorTom Stellard <thomas.stellard@amd.com>2013-08-01 15:23:42 +0000
committerTom Stellard <thomas.stellard@amd.com>2013-08-01 15:23:42 +0000
commit692ee102ebef535d311c35d53457028083e5c5be (patch)
tree5966632bb87e4120a27dadfce4187535429a4275 /lib/Target/R600/AMDGPUCallingConv.td
parent98b357e1cd0d41108e6011725dad6a6dbf208a38 (diff)
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R600: Add 64-bit float load/store support
* Added R600_Reg64 class * Added T#Index#.XY registers definition * Added v2i32 register reads from parameter and global space * Added f32 and i32 elements extraction from v2f32 and v2i32 * Added v2i32 -> v2f32 conversions Tom Stellard: - Mark vec2 operations as expand. The addition of a vec2 register class made them all legal. Patch by: Dmitry Cherkassov Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/AMDGPUCallingConv.td')
-rw-r--r--lib/Target/R600/AMDGPUCallingConv.td10
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/R600/AMDGPUCallingConv.td b/lib/Target/R600/AMDGPUCallingConv.td
index 3865c62..fc95d58 100644
--- a/lib/Target/R600/AMDGPUCallingConv.td
+++ b/lib/Target/R600/AMDGPUCallingConv.td
@@ -38,11 +38,11 @@ def CC_SI : CallingConv<[
// Calling convention for compute kernels
def CC_AMDGPU_Kernel : CallingConv<[
- CCIfType<[v4i32, v4f32], CCAssignToStack <16, 16>>,
- CCIfType<[i64, f64], CCAssignToStack < 8, 8>>,
- CCIfType<[i32, f32], CCAssignToStack < 4, 4>>,
- CCIfType<[i16], CCAssignToStack < 2, 4>>,
- CCIfType<[i8], CCAssignToStack < 1, 4>>
+ CCIfType<[v4i32, v4f32], CCAssignToStack <16, 16>>,
+ CCIfType<[i64, f64, v2f32, v2i32], CCAssignToStack < 8, 8>>,
+ CCIfType<[i32, f32], CCAssignToStack < 4, 4>>,
+ CCIfType<[i16], CCAssignToStack < 2, 4>>,
+ CCIfType<[i8], CCAssignToStack < 1, 4>>
]>;
def CC_AMDGPU : CallingConv<[