R600/SI: Use VSrc_* register classes as the default classes for types

Since the VSrc_* register classes contain both VGPRs and SGPRs, copies
that used be emitted by isel like this:

SGPR = COPY VGPR

Will now be emitted like this:

VSrC = COPY VGPR

This patch also adds a pass that tries to identify and fix situations where
a VGPR to SGPR copy may occur.  Hopefully, these changes will make it
impossible for the compiler to generate illegal VGPR to SGPR copies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187831 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 1 insertions, 23 deletions

diff --git a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
index 38a5f24..f222901 100644
--- a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
+++ b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
@@ -302,7 +302,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
       SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
       SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
     } else if (N->getValueType(0) == MVT::i64) {
-      RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
+      RC = CurDAG->getTargetConstant(AMDGPU::VSrc_64RegClassID, MVT::i32);
       SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
       SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
     } else {
@@ -816,28 +816,6 @@ void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
        E = CurDAG->allnodes_end(); I != E; ++I) {
 
     SDNode *Node = I;
-    switch (Node->getOpcode()) {
-    // Fix the register class in copy to CopyToReg nodes - ISel will always
-    // use SReg classes for 64-bit copies, but this is not always what we want.
-    case ISD::CopyToReg: {
-      unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
-      SDValue Val = Node->getOperand(2);
-      const TargetRegisterClass *RC = RegInfo->getRegClass(Reg);
-      if (RC != &AMDGPU::SReg_64RegClass) {
-        continue;
-      }
-
-      if (!Val.getNode()->isMachineOpcode() ||
-          Val.getNode()->getMachineOpcode() == AMDGPU::IMPLICIT_DEF) {
-        continue;
-      }
-
-      const MCInstrDesc Desc = TM.getInstrInfo()->get(Val.getNode()->getMachineOpcode());
-      const TargetRegisterInfo *TRI = TM.getRegisterInfo();
-      RegInfo->setRegClass(Reg, TRI->getRegClass(Desc.OpInfo[0].RegClass));
-      continue;
-    }
-    }
 
     MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
     if (!MachineNode)