R600: Support for indirect addressing v4

Only implemented for R600 so far.  SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.

At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.

v2:
  - Add support for i8 zext load from stack.
  - Coding style fixes

v3:
  - Don't reserve registers for indirect addressing when it isn't
    being used.
  - Fix bug caused by LLVM limiting the number of SubRegIndex
    declarations.

v4:
  - Fix 64-bit defines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 23 insertions, 0 deletions

diff --git a/lib/Target/R600/AMDGPURegisterInfo.cpp b/lib/Target/R600/AMDGPURegisterInfo.cpp
index b332905..7878d60 100644
--- a/lib/Target/R600/AMDGPURegisterInfo.cpp
+++ b/lib/Target/R600/AMDGPURegisterInfo.cpp
@@ -48,5 +48,28 @@ unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   return 0;
 }
 
+unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const {
+
+  switch(IndirectIndex) {
+  case 0: return AMDGPU::indirect_0;
+  case 1: return AMDGPU::indirect_1;
+  case 2: return AMDGPU::indirect_2;
+  case 3: return AMDGPU::indirect_3;
+  case 4: return AMDGPU::indirect_4;
+  case 5: return AMDGPU::indirect_5;
+  case 6: return AMDGPU::indirect_6;
+  case 7: return AMDGPU::indirect_7;
+  case 8: return AMDGPU::indirect_8;
+  case 9: return AMDGPU::indirect_9;
+  case 10: return AMDGPU::indirect_10;
+  case 11: return AMDGPU::indirect_11;
+  case 12: return AMDGPU::indirect_12;
+  case 13: return AMDGPU::indirect_13;
+  case 14: return AMDGPU::indirect_14;
+  case 15: return AMDGPU::indirect_15;
+  default: llvm_unreachable("indirect index out of range");
+  }
+}
+
 #define GET_REGINFO_TARGET_DESC
 #include "AMDGPUGenRegisterInfo.inc"