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author | Stephen Hines <srhines@google.com> | 2014-04-23 16:57:46 -0700 |
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committer | Stephen Hines <srhines@google.com> | 2014-04-24 15:53:16 -0700 |
commit | 36b56886974eae4f9c5ebc96befd3e7bfe5de338 (patch) | |
tree | e6cfb69fbbd937f450eeb83bfb83b9da3b01275a /lib/Target/R600/AMDGPUTargetMachine.cpp | |
parent | 69a8640022b04415ae9fac62f8ab090601d8f889 (diff) | |
download | external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.zip external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.gz external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.bz2 |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
Diffstat (limited to 'lib/Target/R600/AMDGPUTargetMachine.cpp')
-rw-r--r-- | lib/Target/R600/AMDGPUTargetMachine.cpp | 30 |
1 files changed, 24 insertions, 6 deletions
diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp index bc4f5d7..b11fce3 100644 --- a/lib/Target/R600/AMDGPUTargetMachine.cpp +++ b/lib/Target/R600/AMDGPUTargetMachine.cpp @@ -21,10 +21,10 @@ #include "SIISelLowering.h" #include "SIInstrInfo.h" #include "llvm/Analysis/Passes.h" -#include "llvm/Analysis/Verifier.h" #include "llvm/CodeGen/MachineFunctionAnalysis.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/IR/Verifier.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/PassManager.h" #include "llvm/Support/TargetRegistry.h" @@ -42,13 +42,27 @@ extern "C" void LLVMInitializeR600Target() { } static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) { - return new ScheduleDAGMI(C, new R600SchedStrategy()); + return new ScheduleDAGMILive(C, new R600SchedStrategy()); } static MachineSchedRegistry SchedCustomRegistry("r600", "Run R600's custom scheduler", createR600MachineScheduler); +static std::string computeDataLayout(const AMDGPUSubtarget &ST) { + std::string Ret = "e-p:32:32"; + + if (ST.is64bit()) { + // 32-bit private, local, and region pointers. 64-bit global and constant. + Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64"; + } + + Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256" + "-v512:512-v1024:1024-v2048:2048-n32:64"; + + return Ret; +} + AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, TargetOptions Options, @@ -58,7 +72,7 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT, : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel), Subtarget(TT, CPU, FS), - Layout(Subtarget.getDataLayout()), + Layout(computeDataLayout(Subtarget)), FrameLowering(TargetFrameLowering::StackGrowsUp, 64 * 16 // Maximum stack alignment (long16) , 0), @@ -72,6 +86,7 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT, InstrInfo.reset(new SIInstrInfo(*this)); TLInfo.reset(new SITargetLowering(*this)); } + setRequiresStructuredCFG(true); initAsmInfo(); } @@ -127,7 +142,7 @@ AMDGPUPassConfig::addPreISel() { addPass(createFlattenCFGPass()); if (ST.IsIRStructurizerEnabled()) addPass(createStructurizeCFGPass()); - if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) { + if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) { addPass(createSinkingPass()); addPass(createSITypeRewriter()); addPass(createSIAnnotateControlFlowPass()); @@ -150,6 +165,9 @@ bool AMDGPUPassConfig::addPreRegAlloc() { addPass(createR600VectorRegMerger(*TM)); } else { addPass(createSIFixSGPRCopiesPass(*TM)); + // SIFixSGPRCopies can generate a lot of duplicate instructions, + // so we need to run MachineCSE afterwards. + addPass(&MachineCSEID); } return false; } @@ -167,7 +185,7 @@ bool AMDGPUPassConfig::addPreSched2() { const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(); if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) - addPass(createR600EmitClauseMarkers(*TM)); + addPass(createR600EmitClauseMarkers()); if (ST.isIfCvtEnabled()) addPass(&IfConverterID); if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) @@ -178,7 +196,7 @@ bool AMDGPUPassConfig::addPreSched2() { bool AMDGPUPassConfig::addPreEmitPass() { const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(); if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) { - addPass(createAMDGPUCFGStructurizerPass(*TM)); + addPass(createAMDGPUCFGStructurizerPass()); addPass(createR600ExpandSpecialInstrsPass(*TM)); addPass(&FinalizeMachineBundlesID); addPass(createR600Packetizer(*TM)); |