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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-14 23:24:32 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-14 23:24:32 +0000 |
| commit | 38d5e1c36d954f1ff6489f58efd1d4865217cf9b (patch) | |
| tree | 451454dd8bf6ea5ec2f3ea021da2c7f6de4a928a /lib/Target/R600/R600RegisterInfo.h | |
| parent | 636298ba64fd07d4ddcae6005e7fc1db43eb5335 (diff) | |
| download | external_llvm-38d5e1c36d954f1ff6489f58efd1d4865217cf9b.zip external_llvm-38d5e1c36d954f1ff6489f58efd1d4865217cf9b.tar.gz external_llvm-38d5e1c36d954f1ff6489f58efd1d4865217cf9b.tar.bz2 | |
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG
instructions should make it easier for the register allocator to coalasce
unnecessary copies.
v2:
- Use an SGPR register class if all the operands of BUILD_VECTOR are
SGPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188427 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600RegisterInfo.h')
| -rw-r--r-- | lib/Target/R600/R600RegisterInfo.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/lib/Target/R600/R600RegisterInfo.h b/lib/Target/R600/R600RegisterInfo.h index 9b286ee..d458e55 100644 --- a/lib/Target/R600/R600RegisterInfo.h +++ b/lib/Target/R600/R600RegisterInfo.h @@ -43,10 +43,6 @@ struct R600RegisterInfo : public AMDGPURegisterInfo { /// CFGStructurizer virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const; - /// \returns the sub reg enum value for the given \p Channel - /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sel_x) - unsigned getSubRegFromChannel(unsigned Channel) const; - virtual const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const; }; |