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| author | Vincent Lejeune <vljn@ovi.com> | 2013-10-01 19:32:38 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-10-01 19:32:38 +0000 |
| commit | 5b00e833fabbf5bdf2973c63c39d4a0d0143853a (patch) | |
| tree | 396f9581ca7af7e70bbd9d371bb7cfa628388ce4 /lib/Target/R600/R600RegisterInfo.td | |
| parent | db3de106376558c7425d557b1b980f631107cd14 (diff) | |
| download | external_llvm-5b00e833fabbf5bdf2973c63c39d4a0d0143853a.zip external_llvm-5b00e833fabbf5bdf2973c63c39d4a0d0143853a.tar.gz external_llvm-5b00e833fabbf5bdf2973c63c39d4a0d0143853a.tar.bz2 | |
R600: Enable -verify-machineinstrs in some tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191788 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600RegisterInfo.td')
| -rw-r--r-- | lib/Target/R600/R600RegisterInfo.td | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/R600/R600RegisterInfo.td b/lib/Target/R600/R600RegisterInfo.td index 514427e..6fec43c 100644 --- a/lib/Target/R600/R600RegisterInfo.td +++ b/lib/Target/R600/R600RegisterInfo.td @@ -138,8 +138,6 @@ def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X", def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32, (add OQA, OQB, OQAP, OQBP, LDS_DIRECT_A, LDS_DIRECT_B)>; -} // End isAllocatable = 0 - def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32, (add (sequence "KC0_%u_X", 128, 159))>; @@ -172,6 +170,8 @@ def R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32, (interleave R600_KC1_X, R600_KC1_Y, R600_KC1_Z, R600_KC1_W)>; +} // End isAllocatable = 0 + def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32, (add (sequence "T%u_X", 0, 127), AR_X)>; @@ -192,6 +192,7 @@ def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add R600_TReg32, R600_ArrayBase, R600_Addr, + R600_KC0, R600_KC1, ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF, ALU_CONST, ALU_PARAM, OQAP )>; |