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| author | Vincent Lejeune <vljn@ovi.com> | 2013-02-18 13:48:09 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-02-18 13:48:09 +0000 |
| commit | 628f6d5820aeb00ac1c142c79c5b35c13836de45 (patch) | |
| tree | a98d26986c743fd7a6468e46135a97f9138a936a /lib/Target/R600/R600RegisterInfo.td | |
| parent | 605ff6655b31033dde21e61416751847bd0ee201 (diff) | |
| download | external_llvm-628f6d5820aeb00ac1c142c79c5b35c13836de45.zip external_llvm-628f6d5820aeb00ac1c142c79c5b35c13836de45.tar.gz external_llvm-628f6d5820aeb00ac1c142c79c5b35c13836de45.tar.bz2 | |
R600: Increase number of ArrayBase Reg to 32
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175443 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600RegisterInfo.td')
| -rw-r--r-- | lib/Target/R600/R600RegisterInfo.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/R600/R600RegisterInfo.td b/lib/Target/R600/R600RegisterInfo.td index 3812eb7..0718854 100644 --- a/lib/Target/R600/R600RegisterInfo.td +++ b/lib/Target/R600/R600RegisterInfo.td @@ -44,7 +44,7 @@ foreach Index = 0-127 in { } // Array Base Register holding input in FS -foreach Index = 448-464 in { +foreach Index = 448-480 in { def ArrayBase#Index : R600Reg<"ARRAY_BASE", Index>; } @@ -66,7 +66,7 @@ def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>; def AR_X : R600Reg<"AR.x", 0>; def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32, - (add (sequence "ArrayBase%u", 448, 464))>; + (add (sequence "ArrayBase%u", 448, 480))>; // special registers for ALU src operands // const buffer reference, SRCx_SEL contains index def ALU_CONST : R600Reg<"CBuf", 0>; |