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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-06-03 17:39:54 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-06-03 17:39:54 +0000 |
| commit | b89a467559d3eaade14993c7332afca3539f95d9 (patch) | |
| tree | f0e40d55c94f9a793497ce1872452a268cfeffe0 /lib/Target/R600/SIISelLowering.cpp | |
| parent | 051a28e0e8a5a6f41d9360a58079af6231557152 (diff) | |
| download | external_llvm-b89a467559d3eaade14993c7332afca3539f95d9.zip external_llvm-b89a467559d3eaade14993c7332afca3539f95d9.tar.gz external_llvm-b89a467559d3eaade14993c7332afca3539f95d9.tar.bz2 | |
R600/SI: Handle REG_SEQUENCE in fitsRegClass()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183134 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIISelLowering.cpp')
| -rw-r--r-- | lib/Target/R600/SIISelLowering.cpp | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index d2cf0dc..2526536 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -523,10 +523,20 @@ bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op, if (MachineSDNode *MN = dyn_cast<MachineSDNode>(Node)) { const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode()); int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass; - if (OpClassID == -1) - OpClass = getRegClassFor(Op.getSimpleValueType()); - else + if (OpClassID == -1) { + switch (MN->getMachineOpcode()) { + case AMDGPU::REG_SEQUENCE: + // Operand 0 is the register class id for REG_SEQUENCE instructions. + OpClass = TRI->getRegClass( + cast<ConstantSDNode>(MN->getOperand(0))->getZExtValue()); + break; + default: + OpClass = getRegClassFor(Op.getSimpleValueType()); + break; + } + } else { OpClass = TRI->getRegClass(OpClassID); + } } else if (Node->getOpcode() == ISD::CopyFromReg) { RegisterSDNode *Reg = cast<RegisterSDNode>(Node->getOperand(1).getNode()); |