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| author | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
| commit | ebe69fe11e48d322045d5949c83283927a0d790b (patch) | |
| tree | c92f1907a6b8006628a4b01615f38264d29834ea /lib/Target/R600/SIISelLowering.h | |
| parent | b7d2e72b02a4cb8034f32f8247a2558d2434e121 (diff) | |
| download | external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.zip external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.gz external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.bz2 | |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
Diffstat (limited to 'lib/Target/R600/SIISelLowering.h')
| -rw-r--r-- | lib/Target/R600/SIISelLowering.h | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/lib/Target/R600/SIISelLowering.h b/lib/Target/R600/SIISelLowering.h index 7bf406e..92f5847 100644 --- a/lib/Target/R600/SIISelLowering.h +++ b/lib/Target/R600/SIISelLowering.h @@ -42,27 +42,22 @@ class SITargetLowering : public AMDGPUTargetLowering { SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; - bool foldImm(SDValue &Operand, int32_t &Immediate, - bool &ScalarSlotUsed) const; - const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG, - const SDValue &Op) const; - bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op, - unsigned RegClass) const; - - SDNode *legalizeOperands(MachineSDNode *N, SelectionDAG &DAG) const; void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; - MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const; - static SDValue performUCharToFloatCombine(SDNode *N, - DAGCombinerInfo &DCI); + SDValue performUCharToFloatCombine(SDNode *N, + DAGCombinerInfo &DCI) const; SDValue performSHLPtrCombine(SDNode *N, unsigned AS, DAGCombinerInfo &DCI) const; + SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; + SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; + SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performMin3Max3Combine(SDNode *N, DAGCombinerInfo &DCI) const; + SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; public: - SITargetLowering(TargetMachine &tm); + SITargetLowering(TargetMachine &tm, const AMDGPUSubtarget &STI); bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, EVT /*VT*/) const override; @@ -94,6 +89,7 @@ public: MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI, MachineBasicBlock * BB) const override; + bool enableAggressiveFMAFusion(EVT VT) const override; EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; MVT getScalarShiftAmountTy(EVT VT) const override; bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; |