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author | Tom Stellard <thomas.stellard@amd.com> | 2012-12-11 21:25:42 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2012-12-11 21:25:42 +0000 |
commit | f98f2ce29e6e2996fa58f38979143eceaa818335 (patch) | |
tree | 86dffe7414e6657874db8ac36e5ddcf7d41b2d9c /lib/Target/R600/SIISelLowering.h | |
parent | 57ac1f458a754f30cf500410b438fb260f9b8fe5 (diff) | |
download | external_llvm-f98f2ce29e6e2996fa58f38979143eceaa818335.zip external_llvm-f98f2ce29e6e2996fa58f38979143eceaa818335.tar.gz external_llvm-f98f2ce29e6e2996fa58f38979143eceaa818335.tar.bz2 |
Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIISelLowering.h')
-rw-r--r-- | lib/Target/R600/SIISelLowering.h | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/lib/Target/R600/SIISelLowering.h b/lib/Target/R600/SIISelLowering.h new file mode 100644 index 0000000..27c2a1c --- /dev/null +++ b/lib/Target/R600/SIISelLowering.h @@ -0,0 +1,62 @@ +//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +/// \file +/// \brief SI DAG Lowering interface definition +// +//===----------------------------------------------------------------------===// + +#ifndef SIISELLOWERING_H +#define SIISELLOWERING_H + +#include "AMDGPUISelLowering.h" +#include "SIInstrInfo.h" + +namespace llvm { + +class SITargetLowering : public AMDGPUTargetLowering { + const SIInstrInfo * TII; + + /// Memory reads and writes are syncronized using the S_WAITCNT instruction. + /// This function takes the most conservative approach and inserts an + /// S_WAITCNT instruction after every read and write. + void AppendS_WAITCNT(MachineInstr *MI, MachineBasicBlock &BB, + MachineBasicBlock::iterator I) const; + void LowerMOV_IMM(MachineInstr *MI, MachineBasicBlock &BB, + MachineBasicBlock::iterator I, unsigned Opocde) const; + void LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB, + MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const; + void LowerSI_INTERP_CONST(MachineInstr *MI, MachineBasicBlock &BB, + MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const; + void LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB, + MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const; + void LowerSI_WQM(MachineInstr *MI, MachineBasicBlock &BB, + MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const; + void LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB, + MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const; + + SDValue Loweri1ContextSwitch(SDValue Op, SelectionDAG &DAG, + unsigned VCCNode) const; + SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; + +public: + SITargetLowering(TargetMachine &tm); + virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI, + MachineBasicBlock * BB) const; + virtual EVT getSetCCResultType(EVT VT) const; + virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; + virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; + virtual const char* getTargetNodeName(unsigned Opcode) const; +}; + +} // End namespace llvm + +#endif //SIISELLOWERING_H |