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author | Tom Stellard <thomas.stellard@amd.com> | 2013-11-13 23:36:37 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2013-11-13 23:36:37 +0000 |
commit | b52bf6a3b31596a309f4b12884522e9b4a344654 (patch) | |
tree | 60294ecd3670543e55b24aca1a4507c391649203 /lib/Target/R600/SIInstrFormats.td | |
parent | eef8b8c35c585d941fb14c66df3cebc46b33f776 (diff) | |
download | external_llvm-b52bf6a3b31596a309f4b12884522e9b4a344654.zip external_llvm-b52bf6a3b31596a309f4b12884522e9b4a344654.tar.gz external_llvm-b52bf6a3b31596a309f4b12884522e9b4a344654.tar.bz2 |
R600/SI: Prefer SALU instructions for bit shift operations
All shift operations will be selected as SALU instructions and then
if necessary lowered to VALU instructions in the SIFixSGPRCopies pass.
This allows us to do more operations on the SALU which will improve
performance and is also required for implementing private memory
using indirect addressing, since the private memory pointers must stay
in the scalar registers.
This patch includes some fixes from Matt Arsenault.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIInstrFormats.td')
-rw-r--r-- | lib/Target/R600/SIInstrFormats.td | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td index 962e266..53ebaaf 100644 --- a/lib/Target/R600/SIInstrFormats.td +++ b/lib/Target/R600/SIInstrFormats.td @@ -23,6 +23,7 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> : field bits<1> VOP2 = 0; field bits<1> VOP3 = 0; field bits<1> VOPC = 0; + field bits<1> SALU = 0; let TSFlags{0} = VM_CNT; let TSFlags{1} = EXP_CNT; @@ -33,6 +34,7 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> : let TSFlags{6} = VOP2; let TSFlags{7} = VOP3; let TSFlags{8} = VOPC; + let TSFlags{9} = SALU; } class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> : @@ -67,6 +69,7 @@ class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; + let SALU = 1; } class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : @@ -85,6 +88,7 @@ class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; + let SALU = 1; } class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : @@ -102,6 +106,7 @@ class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; + let SALU = 1; } class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> : @@ -118,6 +123,7 @@ class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> : let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; + let SALU = 1; } class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 < @@ -135,6 +141,7 @@ class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 < let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; + let SALU = 1; } class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm, |