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| author | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
| commit | dce4a407a24b04eebc6a376f8e62b41aaa7b071f (patch) | |
| tree | dcebc53f2b182f145a2e659393bf9a0472cedf23 /lib/Target/R600/SIInstrFormats.td | |
| parent | 220b921aed042f9e520c26cffd8282a94c66c3d5 (diff) | |
| download | external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.zip external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.gz external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.bz2 | |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
Diffstat (limited to 'lib/Target/R600/SIInstrFormats.td')
| -rw-r--r-- | lib/Target/R600/SIInstrFormats.td | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td index aa2c22c..168eff2 100644 --- a/lib/Target/R600/SIInstrFormats.td +++ b/lib/Target/R600/SIInstrFormats.td @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// class InstSI <dag outs, dag ins, string asm, list<dag> pattern> : - AMDGPUInst<outs, ins, asm, pattern> { + AMDGPUInst<outs, ins, asm, pattern>, PredicateControl { field bits<1> VM_CNT = 0; field bits<1> EXP_CNT = 0; @@ -210,16 +210,19 @@ class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> : Enc64 <outs, ins, asm, pattern> { bits<8> dst; + bits<2> src0_modifiers; bits<9> src0; + bits<2> src1_modifiers; bits<9> src1; + bits<2> src2_modifiers; bits<9> src2; - bits<3> abs; bits<1> clamp; bits<2> omod; - bits<3> neg; let Inst{7-0} = dst; - let Inst{10-8} = abs; + let Inst{8} = src0_modifiers{1}; + let Inst{9} = src1_modifiers{1}; + let Inst{10} = src2_modifiers{1}; let Inst{11} = clamp; let Inst{25-17} = op; let Inst{31-26} = 0x34; //encoding @@ -227,7 +230,9 @@ class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> : let Inst{49-41} = src1; let Inst{58-50} = src2; let Inst{60-59} = omod; - let Inst{63-61} = neg; + let Inst{61} = src0_modifiers{0}; + let Inst{62} = src1_modifiers{0}; + let Inst{63} = src2_modifiers{0}; let mayLoad = 0; let mayStore = 0; @@ -240,12 +245,14 @@ class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> : Enc64 <outs, ins, asm, pattern> { bits<8> dst; + bits<2> src0_modifiers; bits<9> src0; + bits<2> src1_modifiers; bits<9> src1; + bits<2> src2_modifiers; bits<9> src2; bits<7> sdst; bits<2> omod; - bits<3> neg; let Inst{7-0} = dst; let Inst{14-8} = sdst; @@ -255,7 +262,9 @@ class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> : let Inst{49-41} = src1; let Inst{58-50} = src2; let Inst{60-59} = omod; - let Inst{63-61} = neg; + let Inst{61} = src0_modifiers{0}; + let Inst{62} = src1_modifiers{0}; + let Inst{63} = src2_modifiers{0}; let mayLoad = 0; let mayStore = 0; |