diff options
| author | Christian Konig <christian.koenig@amd.com> | 2013-02-16 11:28:30 +0000 |
|---|---|---|
| committer | Christian Konig <christian.koenig@amd.com> | 2013-02-16 11:28:30 +0000 |
| commit | e9ba1830df2efef3da113a740909195e839ebd36 (patch) | |
| tree | 93e772de9a442b7fa9fe4e13b73b3d8a8223a3cc /lib/Target/R600/SIInstrFormats.td | |
| parent | e25e490793241e471036c3e2f969ce6a068e5ce1 (diff) | |
| download | external_llvm-e9ba1830df2efef3da113a740909195e839ebd36.zip external_llvm-e9ba1830df2efef3da113a740909195e839ebd36.tar.gz external_llvm-e9ba1830df2efef3da113a740909195e839ebd36.tar.bz2 | |
R600/SI: nuke SReg_1 v3
It's completely unnecessary and can be replace with proper
SReg_64 handling instead.
This actually fixes a piglit test on SI.
v2: use correct register class in addRegisterClass,
set special classes as not allocatable
v3: revert setting special classes as not allocateable
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175355 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIInstrFormats.td')
| -rw-r--r-- | lib/Target/R600/SIInstrFormats.td | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td index 5c69c15..40e37aa 100644 --- a/lib/Target/R600/SIInstrFormats.td +++ b/lib/Target/R600/SIInstrFormats.td @@ -39,9 +39,6 @@ class SOP2_32 <bits<7> op, string opName, list<dag> pattern> class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>; -class SOP2_VCC <bits<7> op, string opName, list<dag> pattern> - : SOP2 <op, (outs SReg_1:$vcc), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>; - class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, string opName, list<dag> pattern> : VOP1 < @@ -101,7 +98,7 @@ multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, def _e32 : VOPC <op, (ins arc:$src0, vrc:$src1), opName, pattern>; def _e64 : VOP3 < {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - (outs SReg_1:$dst), + (outs SReg_64:$dst), (ins arc:$src0, vrc:$src1, InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), |