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| author | Christian Konig <christian.koenig@amd.com> | 2013-02-26 17:52:09 +0000 |
|---|---|---|
| committer | Christian Konig <christian.koenig@amd.com> | 2013-02-26 17:52:09 +0000 |
| commit | 749428f852b63a98e872ba69b0c576b26b7b7518 (patch) | |
| tree | d86e8c9b5598ad38bec01f645a9e6aaa33bcffb2 /lib/Target/R600/SIInstrInfo.td | |
| parent | 6fd49bc89adb515ae389f34f18b3c52c13b579fa (diff) | |
| download | external_llvm-749428f852b63a98e872ba69b0c576b26b7b7518.zip external_llvm-749428f852b63a98e872ba69b0c576b26b7b7518.tar.gz external_llvm-749428f852b63a98e872ba69b0c576b26b7b7518.tar.bz2 | |
R600/SI: fix VOP3b encoding v2
v2: document why we hardcode VCC for now.
This is a candidate for the mesa-stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176099 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIInstrInfo.td')
| -rw-r--r-- | lib/Target/R600/SIInstrInfo.td | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 99168ce..d68fbff 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -51,6 +51,7 @@ class InlineImm <ValueType vt> : ImmLeaf <vt, [{ def SIOperand { int ZERO = 0x80; + int VCC = 0x6A; } class GPR4Align <RegisterClass rc> : Operand <vAny> { @@ -195,6 +196,29 @@ multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> : VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>; +multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern> { + + def _e32 : VOP2 < + op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1), + opName#"_e32 $dst, $src0, $src1", pattern + >; + + def _e64 : VOP3b < + {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + (outs VReg_32:$dst), + (ins VSrc_32:$src0, VReg_32:$src1, + i32imm:$abs, i32imm:$clamp, + i32imm:$omod, i32imm:$neg), + opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", [] + > { + let SRC2 = SIOperand.ZERO; + /* the VOP2 variant puts the carry out into VCC, the VOP3 variant + can write it into any SGPR. We currently don't use the carry out, + so for now hardcode it to VCC as well */ + let SDST = SIOperand.VCC; + } +} + multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, string opName, ValueType vt, PatLeaf cond> { |