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| author | Christian Konig <christian.koenig@amd.com> | 2013-02-21 15:17:04 +0000 |
|---|---|---|
| committer | Christian Konig <christian.koenig@amd.com> | 2013-02-21 15:17:04 +0000 |
| commit | 7b3dab2673128257b6bf9a3eaa4fe5aad9c9a675 (patch) | |
| tree | 23443362fedd2cd15cfab78c07708b13fffaa614 /lib/Target/R600/SIInstrInfo.td | |
| parent | 477963aff4f7fd93c3dfdb253c2983dc9f0450f9 (diff) | |
| download | external_llvm-7b3dab2673128257b6bf9a3eaa4fe5aad9c9a675.zip external_llvm-7b3dab2673128257b6bf9a3eaa4fe5aad9c9a675.tar.gz external_llvm-7b3dab2673128257b6bf9a3eaa4fe5aad9c9a675.tar.bz2 | |
R600/SI: simplify VOPC_* pattern v2
Fixing asm operation names.
v2: fix name of the e64 encoding, also add asm operands
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175750 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIInstrInfo.td')
| -rw-r--r-- | lib/Target/R600/SIInstrInfo.td | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index dc18a71..0808f24 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -194,26 +194,35 @@ multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> : VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>; multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, - string opName, list<dag> pattern> { + string opName, ValueType vt, PatLeaf cond> { + + def _e32 : VOPC < + op, (ins arc:$src0, vrc:$src1), + opName#"_e32 $dst, $src0, $src1", [] + >; - def _e32 : VOPC <op, (ins arc:$src0, vrc:$src1), opName, pattern>; def _e64 : VOP3 < {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, (outs SReg_64:$dst), (ins arc:$src0, vrc:$src1, InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), - opName, pattern + opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", + !if(!eq(!cast<string>(cond), "COND_NULL"), []<dag>, + [(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), vrc:$src1, cond)))] + ) > { let SRC2 = SIOperand.ZERO; } } -multiclass VOPC_32 <bits<8> op, string opName, list<dag> pattern> - : VOPC_Helper <op, VReg_32, VSrc_32, opName, pattern>; +multiclass VOPC_32 <bits<8> op, string opName, + ValueType vt = untyped, PatLeaf cond = COND_NULL> + : VOPC_Helper <op, VReg_32, VSrc_32, opName, vt, cond>; -multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern> - : VOPC_Helper <op, VReg_64, VSrc_64, opName, pattern>; +multiclass VOPC_64 <bits<8> op, string opName, + ValueType vt = untyped, PatLeaf cond = COND_NULL> + : VOPC_Helper <op, VReg_64, VSrc_64, opName, vt, cond>; //===----------------------------------------------------------------------===// // Vector I/O classes |