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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:12:20 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:12:20 +0000 |
| commit | a6a39ced095c2f453624ce62c4aead25db41a18f (patch) | |
| tree | b7ae0e904a814233601cf7c343a860bbf5f64809 /lib/Target/R600/SIInstrInfo.td | |
| parent | 30d84d8dfa0433088d541c66b92af0da3855bc9c (diff) | |
| download | external_llvm-a6a39ced095c2f453624ce62c4aead25db41a18f.zip external_llvm-a6a39ced095c2f453624ce62c4aead25db41a18f.tar.gz external_llvm-a6a39ced095c2f453624ce62c4aead25db41a18f.tar.bz2 | |
R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions
The SIInsertWaits pass was overwriting the first operand (gds bit) of
DS_WRITE_B32 with the second operand (value to write). This meant that
any time the value to write was stored in an odd number VGPR, the gds
bit would be set causing the instruction to write to GDS instead of LDS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188522 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIInstrInfo.td')
| -rw-r--r-- | lib/Target/R600/SIInstrInfo.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index ecc4718..1965ba0 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -342,8 +342,8 @@ class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 < class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS < op, (outs regClass:$vdst), - (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1, - i8imm:$offset0, i8imm:$offset1), + (ins VReg_32:$addr, VReg_32:$data0, VReg_32:$data1, + i8imm:$offset0, i8imm:$offset1, i1imm:$gds), asm#" $vdst, $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]", []> { let mayLoad = 1; @@ -353,8 +353,8 @@ class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS < class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS < op, (outs), - (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1, - i8imm:$offset0, i8imm:$offset1), + (ins VReg_32:$addr, VReg_32:$data0, VReg_32:$data1, + i8imm:$offset0, i8imm:$offset1, i1imm:$gds), asm#" $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]", []> { let mayStore = 1; |