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| author | Stephen Hines <srhines@google.com> | 2013-05-02 16:19:29 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2013-05-02 16:19:29 -0700 |
| commit | 38578c4919ea18ceb27e29988b2d857afe6215bf (patch) | |
| tree | 6718ee1e6a1a59f46b6c847439ebfcd291c1e393 /lib/Target/R600/SILowerControlFlow.cpp | |
| parent | ffb69c62ac54b0af5768ae9486b93b39a6c6b94c (diff) | |
| parent | a7a05ee70cb07f32996a0587a636b406c746b71b (diff) | |
| download | external_llvm-38578c4919ea18ceb27e29988b2d857afe6215bf.zip external_llvm-38578c4919ea18ceb27e29988b2d857afe6215bf.tar.gz external_llvm-38578c4919ea18ceb27e29988b2d857afe6215bf.tar.bz2 | |
Merge remote-tracking branch 'upstream/master' into merge-20130502
Conflicts:
lib/Support/Unix/Signals.inc
unittests/Transforms/Utils/Cloning.cpp
Change-Id: I027581a4390ec3ce4cd8d33da8b5f4c0c7d372c8
Diffstat (limited to 'lib/Target/R600/SILowerControlFlow.cpp')
| -rw-r--r-- | lib/Target/R600/SILowerControlFlow.cpp | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/lib/Target/R600/SILowerControlFlow.cpp b/lib/Target/R600/SILowerControlFlow.cpp index 9a027e7..2b60eb9 100644 --- a/lib/Target/R600/SILowerControlFlow.cpp +++ b/lib/Target/R600/SILowerControlFlow.cpp @@ -197,7 +197,8 @@ void SILowerControlFlowPass::Else(MachineInstr &MI) { unsigned Dst = MI.getOperand(0).getReg(); unsigned Src = MI.getOperand(1).getReg(); - BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst) + BuildMI(MBB, MBB.getFirstNonPHI(), DL, + TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst) .addReg(Src); // Saved EXEC BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC) @@ -409,6 +410,7 @@ void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) { bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) { bool HaveKill = false; + bool NeedWQM = false; unsigned Depth = 0; for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); @@ -478,9 +480,22 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) { case AMDGPU::SI_INDIRECT_DST_V16: IndirectDst(MI); break; + + case AMDGPU::V_INTERP_P1_F32: + case AMDGPU::V_INTERP_P2_F32: + case AMDGPU::V_INTERP_MOV_F32: + NeedWQM = true; + break; + } } } + if (NeedWQM) { + MachineBasicBlock &MBB = MF.front(); + BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64), + AMDGPU::EXEC).addReg(AMDGPU::EXEC); + } + return true; } |