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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-02-07 17:02:09 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-02-07 17:02:09 +0000 |
| commit | 36ba9091843bd1205fe3499ba4b55bbedc6583c9 (patch) | |
| tree | 257e498147cbf69d6548526534c626e005cdf300 /lib/Target/R600/SIRegisterInfo.td | |
| parent | 66f535a273e52d56199c7ce8f975796017b6cbb2 (diff) | |
| download | external_llvm-36ba9091843bd1205fe3499ba4b55bbedc6583c9.zip external_llvm-36ba9091843bd1205fe3499ba4b55bbedc6583c9.tar.gz external_llvm-36ba9091843bd1205fe3499ba4b55bbedc6583c9.tar.bz2 | |
R600/SI: Add basic support for more integer vector types.
v1i32, v2i32, v8i32 and v16i32.
Only add VGPR register classes for integer vector types, to avoid attempts
copying from VGPR to SGPR registers, which is not possible.
Patch By: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174632 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIRegisterInfo.td')
| -rw-r--r-- | lib/Target/R600/SIRegisterInfo.td | 41 |
1 files changed, 38 insertions, 3 deletions
diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td index a1c7a86..9b483eb 100644 --- a/lib/Target/R600/SIRegisterInfo.td +++ b/lib/Target/R600/SIRegisterInfo.td @@ -101,6 +101,37 @@ def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3], (add (rotl VGPR_32, 2)), (add (rotl VGPR_32, 3))]>; +// VGPR 256-bit registers +def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7], + [(add VGPR_32), + (add (rotl VGPR_32, 1)), + (add (rotl VGPR_32, 2)), + (add (rotl VGPR_32, 3)), + (add (rotl VGPR_32, 4)), + (add (rotl VGPR_32, 5)), + (add (rotl VGPR_32, 6)), + (add (rotl VGPR_32, 7))]>; + +// VGPR 512-bit registers +def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, + sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15], + [(add VGPR_32), + (add (rotl VGPR_32, 1)), + (add (rotl VGPR_32, 2)), + (add (rotl VGPR_32, 3)), + (add (rotl VGPR_32, 4)), + (add (rotl VGPR_32, 5)), + (add (rotl VGPR_32, 6)), + (add (rotl VGPR_32, 7)), + (add (rotl VGPR_32, 8)), + (add (rotl VGPR_32, 9)), + (add (rotl VGPR_32, 10)), + (add (rotl VGPR_32, 11)), + (add (rotl VGPR_32, 12)), + (add (rotl VGPR_32, 13)), + (add (rotl VGPR_32, 14)), + (add (rotl VGPR_32, 15))]>; + // Register class for all scalar registers (SGPRs + Special Registers) def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, (add SGPR_32, SREG_LIT_0, M0, EXEC_LO, EXEC_HI) @@ -115,7 +146,7 @@ def SReg_128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add SGPR_128)>; def SReg_256 : RegisterClass<"AMDGPU", [v8i32], 256, (add SGPR_256)>; // Register class for all vector registers (VGPRs + Interploation Registers) -def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, +def VReg_32 : RegisterClass<"AMDGPU", [f32, i32, v1i32], 32, (add VGPR_32, PERSP_SAMPLE_I, PERSP_SAMPLE_J, PERSP_CENTER_I, PERSP_CENTER_J, @@ -136,9 +167,13 @@ def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, ) >; -def VReg_64 : RegisterClass<"AMDGPU", [i64], 64, (add VGPR_64)>; +def VReg_64 : RegisterClass<"AMDGPU", [i64, v2i32], 64, (add VGPR_64)>; + +def VReg_128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add VGPR_128)>; + +def VReg_256 : RegisterClass<"AMDGPU", [v8i32], 256, (add VGPR_256)>; -def VReg_128 : RegisterClass<"AMDGPU", [v4f32], 128, (add VGPR_128)>; +def VReg_512 : RegisterClass<"AMDGPU", [v16i32], 512, (add VGPR_512)>; // AllReg_* - A set of all scalar and vector registers of a given width. def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, (add VReg_32, SReg_32)>; |