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| author | Tom Stellard <thomas.stellard@amd.com> | 2012-12-19 22:10:34 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2012-12-19 22:10:34 +0000 |
| commit | 45f75be5649c50e2e3f71513a72e95534d7c9a18 (patch) | |
| tree | 5a8dbb194f322957c3820d1d13b2a64b32301661 /lib/Target/R600/SIRegisterInfo.td | |
| parent | d09d43ae53e1eba83dc5516a148748001b8ff812 (diff) | |
| download | external_llvm-45f75be5649c50e2e3f71513a72e95534d7c9a18.zip external_llvm-45f75be5649c50e2e3f71513a72e95534d7c9a18.tar.gz external_llvm-45f75be5649c50e2e3f71513a72e95534d7c9a18.tar.bz2 | |
R600: Remove unecessary VREG alignment.
Unlike SGPRs VGPRs doesn't need to be aligned.
Patch by: Christian König
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170593 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIRegisterInfo.td')
| -rw-r--r-- | lib/Target/R600/SIRegisterInfo.td | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td index e52311a..c3f1361 100644 --- a/lib/Target/R600/SIRegisterInfo.td +++ b/lib/Target/R600/SIRegisterInfo.td @@ -105,15 +105,15 @@ def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32, // VGPR 64-bit registers def VGPR_64 : RegisterTuples<[low, high], - [(add (decimate VGPR_32, 2)), - (add (decimate (rotl VGPR_32, 1), 2))]>; + [(add VGPR_32), + (add (rotl VGPR_32, 1))]>; // VGPR 128-bit registers def VGPR_128 : RegisterTuples<[sel_x, sel_y, sel_z, sel_w], - [(add (decimate VGPR_32, 4)), - (add (decimate (rotl VGPR_32, 1), 4)), - (add (decimate (rotl VGPR_32, 2), 4)), - (add (decimate (rotl VGPR_32, 3), 4))]>; + [(add VGPR_32), + (add (rotl VGPR_32, 1)), + (add (rotl VGPR_32, 2)), + (add (rotl VGPR_32, 3))]>; // Register class for all scalar registers (SGPRs + Special Registers) def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, |