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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-10-10 17:11:55 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-10-10 17:11:55 +0000 |
| commit | 47fbbc2dc5696d27f4e3c8a5432777976dd8da0a (patch) | |
| tree | 096a79c4184a6ac2c9f710bebe924131ffbdd93a /lib/Target/R600/SIRegisterInfo.td | |
| parent | 39867850462b1eefd76510e25bca4f2a51f65a70 (diff) | |
| download | external_llvm-47fbbc2dc5696d27f4e3c8a5432777976dd8da0a.zip external_llvm-47fbbc2dc5696d27f4e3c8a5432777976dd8da0a.tar.gz external_llvm-47fbbc2dc5696d27f4e3c8a5432777976dd8da0a.tar.bz2 | |
R600/SI: Implement SIInstrInfo::verifyInstruction() for VOP*
The function is used by the machine verifier and checks that VOP*
instructions have legal operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192367 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIRegisterInfo.td')
| -rw-r--r-- | lib/Target/R600/SIRegisterInfo.td | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td index 0b90772..2d7bff0 100644 --- a/lib/Target/R600/SIRegisterInfo.td +++ b/lib/Target/R600/SIRegisterInfo.td @@ -43,7 +43,7 @@ def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32, (add (sequence "SGPR%u", 0, 101))>; // SGPR 64-bit registers -def SGPR_64 : RegisterTuples<[sub0, sub1], +def SGPR_64Regs : RegisterTuples<[sub0, sub1], [(add (decimate (trunc SGPR_32, 101), 2)), (add (decimate (shl SGPR_32, 1), 2))]>; @@ -153,8 +153,10 @@ def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, (add SGPR_32, M0Reg) >; +def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64], 64, (add SGPR_64Regs)>; + def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, i1], 64, - (add SGPR_64, VCCReg, EXECReg) + (add SGPR_64Regs, VCCReg, EXECReg) >; def SReg_128 : RegisterClass<"AMDGPU", [i128], 128, (add SGPR_128)>; |