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| author | Christian Konig <christian.koenig@amd.com> | 2013-04-10 08:39:16 +0000 |
|---|---|---|
| committer | Christian Konig <christian.koenig@amd.com> | 2013-04-10 08:39:16 +0000 |
| commit | 4d0e8a8a3e2e5b98f598acad4d57452b99d52e74 (patch) | |
| tree | b02888c7d78ff0841f6ab4668192c8b754d2defd /lib/Target/R600/SIRegisterInfo.td | |
| parent | 84a775d8e3d5a3765e01db4b454f849ed8be99be (diff) | |
| download | external_llvm-4d0e8a8a3e2e5b98f598acad4d57452b99d52e74.zip external_llvm-4d0e8a8a3e2e5b98f598acad4d57452b99d52e74.tar.gz external_llvm-4d0e8a8a3e2e5b98f598acad4d57452b99d52e74.tar.bz2 | |
R600/SI: dynamical figure out the reg class of MIMG
Depending on the number of bits set in the writemask.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179166 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIRegisterInfo.td')
| -rw-r--r-- | lib/Target/R600/SIRegisterInfo.td | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td index 2c10107..244d4c0 100644 --- a/lib/Target/R600/SIRegisterInfo.td +++ b/lib/Target/R600/SIRegisterInfo.td @@ -94,6 +94,12 @@ def VGPR_64 : RegisterTuples<[sub0, sub1], [(add (trunc VGPR_32, 255)), (add (shl VGPR_32, 1))]>; +// VGPR 96-bit registers +def VGPR_96 : RegisterTuples<[sub0, sub1, sub2], + [(add (trunc VGPR_32, 254)), + (add (shl VGPR_32, 1)), + (add (shl VGPR_32, 2))]>; + // VGPR 128-bit registers def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3], [(add (trunc VGPR_32, 253)), @@ -162,6 +168,10 @@ def VReg_32 : RegisterClass<"AMDGPU", [i32, f32, v1i32], 32, (add VGPR_32)>; def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 64, (add VGPR_64)>; +def VReg_96 : RegisterClass<"AMDGPU", [untyped], 96, (add VGPR_96)> { + let Size = 96; +} + def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128, (add VGPR_128)>; def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 256, (add VGPR_256)>; |