diff options
| author | Christian Konig <christian.koenig@amd.com> | 2013-02-16 11:28:13 +0000 |
|---|---|---|
| committer | Christian Konig <christian.koenig@amd.com> | 2013-02-16 11:28:13 +0000 |
| commit | 8e4eebcecf291386a321d0f8582b8a57841ea8c9 (patch) | |
| tree | 89a18ef31383a6c7abfa6a0d9b0d00837d29dd71 /lib/Target/R600/SIRegisterInfo.td | |
| parent | 305fefbb65c3df7bf5b3a8f6157efe24652c1e56 (diff) | |
| download | external_llvm-8e4eebcecf291386a321d0f8582b8a57841ea8c9.zip external_llvm-8e4eebcecf291386a321d0f8582b8a57841ea8c9.tar.gz external_llvm-8e4eebcecf291386a321d0f8582b8a57841ea8c9.tar.bz2 | |
R600/SI: replace AllReg_* with [SV]Src_* v2
Mark all the operands that can also have an immediate.
v2: SOFFSET is also an SSrc_32 operand
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175353 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIRegisterInfo.td')
| -rw-r--r-- | lib/Target/R600/SIRegisterInfo.td | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td index 809d503..150c92e 100644 --- a/lib/Target/R600/SIRegisterInfo.td +++ b/lib/Target/R600/SIRegisterInfo.td @@ -177,10 +177,14 @@ def VReg_256 : RegisterClass<"AMDGPU", [v8i32], 256, (add VGPR_256)>; def VReg_512 : RegisterClass<"AMDGPU", [v16i32], 512, (add VGPR_512)>; -// AllReg_* - A set of all scalar and vector registers of a given width. -def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, (add VReg_32, SReg_32)>; +// [SV]Src_* operands can have either an immediate or an register +def SSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add SReg_32)>; -def AllReg_64 : RegisterClass<"AMDGPU", [f64, i64], 64, (add SReg_64, VReg_64)>; +def SSrc_64 : RegisterClass<"AMDGPU", [i64], 64, (add SReg_64)>; + +def VSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VReg_32, SReg_32)>; + +def VSrc_64 : RegisterClass<"AMDGPU", [i64], 64, (add SReg_64, VReg_64)>; // Special register classes for predicates and the M0 register def SCCReg : RegisterClass<"AMDGPU", [i1], 1, (add SCC)>; |