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| author | Christian Konig <christian.koenig@amd.com> | 2013-02-21 15:16:58 +0000 |
|---|---|---|
| committer | Christian Konig <christian.koenig@amd.com> | 2013-02-21 15:16:58 +0000 |
| commit | 477963aff4f7fd93c3dfdb253c2983dc9f0450f9 (patch) | |
| tree | ecb1f3e1ec1916ecf2224097665a3602d09d62f9 /lib/Target/R600 | |
| parent | a38ccb4b32fca60264b734090a00cb850bcfbaf7 (diff) | |
| download | external_llvm-477963aff4f7fd93c3dfdb253c2983dc9f0450f9.zip external_llvm-477963aff4f7fd93c3dfdb253c2983dc9f0450f9.tar.gz external_llvm-477963aff4f7fd93c3dfdb253c2983dc9f0450f9.tar.bz2 | |
R600/SI: rework VOP2_* pattern v2
Fixing asm operation names.
v2: use ZERO constant, also add asm operands
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175749 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600')
| -rw-r--r-- | lib/Target/R600/SIISelLowering.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/R600/SIInstrInfo.td | 37 |
2 files changed, 19 insertions, 21 deletions
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index 4085890..5a468ae 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -75,7 +75,6 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( .addOperand(MI->getOperand(0)) .addOperand(MI->getOperand(1)) .addImm(0x80) // SRC1 - .addImm(0x80) // SRC2 .addImm(0) // ABS .addImm(1) // CLAMP .addImm(0) // OMOD @@ -88,7 +87,6 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( .addOperand(MI->getOperand(0)) .addOperand(MI->getOperand(1)) .addImm(0x80) // SRC1 - .addImm(0x80) // SRC2 .addImm(1) // ABS .addImm(0) // CLAMP .addImm(0) // OMOD @@ -101,7 +99,6 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( .addOperand(MI->getOperand(0)) .addOperand(MI->getOperand(1)) .addImm(0x80) // SRC1 - .addImm(0x80) // SRC2 .addImm(0) // ABS .addImm(0) // CLAMP .addImm(0) // OMOD diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 2b31307..dc18a71 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -168,29 +168,30 @@ multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern> : VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>; -class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc, - string opName, list<dag> pattern> : - VOP2 < - op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern +multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc, + string opName, list<dag> pattern> { + def _e32 : VOP2 < + op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), + opName#"_e32 $dst, $src0, $src1", pattern >; -multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> { - - def _e32 : VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern>; - - def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - opName, [] - >; + def _e64 : VOP3 < + {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + (outs vrc:$dst), + (ins arc:$src0, vrc:$src1, + i32imm:$abs, i32imm:$clamp, + i32imm:$omod, i32imm:$neg), + opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", [] + > { + let SRC2 = SIOperand.ZERO; + } } -multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> { - def _e32: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>; +multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> + : VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern>; - def _e64 : VOP3_64 < - {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - opName, [] - >; -} +multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> + : VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>; multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, string opName, list<dag> pattern> { |