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author | Tom Stellard <thomas.stellard@amd.com> | 2013-04-19 02:11:06 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2013-04-19 02:11:06 +0000 |
commit | 48b809e6e5cf4a7d1b876ac1d56a9e32df506f76 (patch) | |
tree | 962ac5fe49ace84ae12af3f41b9a29efa4eafa94 /lib/Target/R600 | |
parent | ae2a8929d890424193394ac63a1a21292a216d7a (diff) | |
download | external_llvm-48b809e6e5cf4a7d1b876ac1d56a9e32df506f76.zip external_llvm-48b809e6e5cf4a7d1b876ac1d56a9e32df506f76.tar.gz external_llvm-48b809e6e5cf4a7d1b876ac1d56a9e32df506f76.tar.bz2 |
R600: Add pattern for the BFI_INT instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179830 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600')
-rw-r--r-- | lib/Target/R600/AMDGPUInstructions.td | 20 | ||||
-rw-r--r-- | lib/Target/R600/R600Instructions.td | 3 | ||||
-rw-r--r-- | lib/Target/R600/SIInstructions.td | 1 |
3 files changed, 24 insertions, 0 deletions
diff --git a/lib/Target/R600/AMDGPUInstructions.td b/lib/Target/R600/AMDGPUInstructions.td index fa890c1..4b37a53 100644 --- a/lib/Target/R600/AMDGPUInstructions.td +++ b/lib/Target/R600/AMDGPUInstructions.td @@ -261,6 +261,26 @@ class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat < (vt rc:$addr) >; +// BFI_INT patterns + +multiclass BFIPatterns <Instruction BFI_INT> { + + // Definition from ISA doc: + // (y & x) | (z & ~x) + def : Pat < + (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))), + (BFI_INT $x, $y, $z) + >; + + // SHA-256 Ch function + // z ^ (x & (y ^ z)) + def : Pat < + (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))), + (BFI_INT $x, $y, $z) + >; + +} + include "R600Instructions.td" include "SIInstrInfo.td" diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td index da8228d..361fc98 100644 --- a/lib/Target/R600/R600Instructions.td +++ b/lib/Target/R600/R600Instructions.td @@ -1570,6 +1570,9 @@ let Predicates = [isEGorCayman] in { VecALU >; + def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", []>; + defm : BFIPatterns <BFI_INT_eg>; + def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))], diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 2ab3486..9faf89b 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -948,6 +948,7 @@ def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>; def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>; def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>; +defm : BFIPatterns <V_BFI_B32>; def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", []>; def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", []>; //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; |