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author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:11:55 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:11:55 +0000 |
commit | 6b88cdb34cc78f815946b8ebe6c2332d084526ad (patch) | |
tree | 102bb8a37ee9934f8a15d64e0f44d92ff61be8ae /lib/Target/R600 | |
parent | e7ac2ed1c268891a856ab38db1e34372a79da86a (diff) | |
download | external_llvm-6b88cdb34cc78f815946b8ebe6c2332d084526ad.zip external_llvm-6b88cdb34cc78f815946b8ebe6c2332d084526ad.tar.gz external_llvm-6b88cdb34cc78f815946b8ebe6c2332d084526ad.tar.bz2 |
R600: Enable folding of inline literals into REQ_SEQUENCE instructions
Tested-by: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188517 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600')
-rw-r--r-- | lib/Target/R600/AMDGPUISelDAGToDAG.cpp | 37 | ||||
-rw-r--r-- | lib/Target/R600/R600OptimizeVectorRegisters.cpp | 3 |
2 files changed, 23 insertions, 17 deletions
diff --git a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp index 77ca885..4f78f29 100644 --- a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp +++ b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp @@ -453,29 +453,32 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) { continue; } } else { - if (!TII->isALUInstr(Use->getMachineOpcode()) || - (TII->get(Use->getMachineOpcode()).TSFlags & - R600_InstFlag::VECTOR)) { - continue; - } - - int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(), - AMDGPU::OpName::literal); - if (ImmIdx == -1) { - continue; - } - - if (TII->getOperandIdx(Use->getMachineOpcode(), - AMDGPU::OpName::dst) != -1) { - // subtract one from ImmIdx, because the DST operand is usually index - // 0 for MachineInstrs, but we have no DST in the Ops vector. - ImmIdx--; + switch(Use->getMachineOpcode()) { + case AMDGPU::REG_SEQUENCE: break; + default: + if (!TII->isALUInstr(Use->getMachineOpcode()) || + (TII->get(Use->getMachineOpcode()).TSFlags & + R600_InstFlag::VECTOR)) { + continue; + } } // Check that we aren't already using an immediate. // XXX: It's possible for an instruction to have more than one // immediate operand, but this is not supported yet. if (ImmReg == AMDGPU::ALU_LITERAL_X) { + int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(), + AMDGPU::OpName::literal); + if (ImmIdx == -1) { + continue; + } + + if (TII->getOperandIdx(Use->getMachineOpcode(), + AMDGPU::OpName::dst) != -1) { + // subtract one from ImmIdx, because the DST operand is usually index + // 0 for MachineInstrs, but we have no DST in the Ops vector. + ImmIdx--; + } ConstantSDNode *C = dyn_cast<ConstantSDNode>(Use->getOperand(ImmIdx)); assert(C); diff --git a/lib/Target/R600/R600OptimizeVectorRegisters.cpp b/lib/Target/R600/R600OptimizeVectorRegisters.cpp index acacffa..cf719c0 100644 --- a/lib/Target/R600/R600OptimizeVectorRegisters.cpp +++ b/lib/Target/R600/R600OptimizeVectorRegisters.cpp @@ -50,6 +50,9 @@ isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { E = MRI.def_end(); It != E; ++It) { return (*It).isImplicitDef(); } + if (MRI.isReserved(Reg)) { + return false; + } llvm_unreachable("Reg without a def"); return false; } |