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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:18:43 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:18:43 +0000 |
| commit | b07ec9606813cf16b137f0bb9ce09ca7ce57f026 (patch) | |
| tree | 2674dfd7f9aca32e97da4be172600c63d1b40294 /lib/Target/R600 | |
| parent | a6a39ced095c2f453624ce62c4aead25db41a18f (diff) | |
| download | external_llvm-b07ec9606813cf16b137f0bb9ce09ca7ce57f026.zip external_llvm-b07ec9606813cf16b137f0bb9ce09ca7ce57f026.tar.gz external_llvm-b07ec9606813cf16b137f0bb9ce09ca7ce57f026.tar.bz2 | |
Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions"
This reverts commit a6a39ced095c2f453624ce62c4aead25db41a18f.
This is the wrong version of this fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188523 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600')
| -rw-r--r-- | lib/Target/R600/SIInsertWaits.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/R600/SIInstrInfo.td | 8 | ||||
| -rw-r--r-- | lib/Target/R600/SIInstructions.td | 6 |
3 files changed, 10 insertions, 8 deletions
diff --git a/lib/Target/R600/SIInsertWaits.cpp b/lib/Target/R600/SIInsertWaits.cpp index c477be5..ba202e3 100644 --- a/lib/Target/R600/SIInsertWaits.cpp +++ b/lib/Target/R600/SIInsertWaits.cpp @@ -134,7 +134,9 @@ Counters SIInsertWaits::getHwCounts(MachineInstr &MI) { // LGKM may uses larger values if (TSFlags & SIInstrFlags::LGKM_CNT) { - const MachineOperand &Op = MI.getOperand(0); + MachineOperand &Op = MI.getOperand(0); + if (!Op.isReg()) + Op = MI.getOperand(1); assert(Op.isReg() && "First LGKM operand must be a register!"); unsigned Reg = Op.getReg(); diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 1965ba0..ecc4718 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -342,8 +342,8 @@ class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 < class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS < op, (outs regClass:$vdst), - (ins VReg_32:$addr, VReg_32:$data0, VReg_32:$data1, - i8imm:$offset0, i8imm:$offset1, i1imm:$gds), + (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1, + i8imm:$offset0, i8imm:$offset1), asm#" $vdst, $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]", []> { let mayLoad = 1; @@ -353,8 +353,8 @@ class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS < class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS < op, (outs), - (ins VReg_32:$addr, VReg_32:$data0, VReg_32:$data1, - i8imm:$offset0, i8imm:$offset1, i1imm:$gds), + (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1, + i8imm:$offset0, i8imm:$offset1), asm#" $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]", []> { let mayStore = 1; diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 9856fa6..4eb3566 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1745,13 +1745,13 @@ def : Pat < def : Pat < (local_load i64:$src0), - (i32 (DS_READ_B32 (EXTRACT_SUBREG $src0, sub0), - (EXTRACT_SUBREG $src0, sub0), (EXTRACT_SUBREG $src0, sub0), 0, 0, 0)) + (i32 (DS_READ_B32 0, (EXTRACT_SUBREG $src0, sub0), + (EXTRACT_SUBREG $src0, sub0), (EXTRACT_SUBREG $src0, sub0), 0, 0)) >; def : Pat < (local_store i32:$src1, i64:$src0), - (DS_WRITE_B32 (EXTRACT_SUBREG $src0, sub0), $src1, $src1, 0, 0, 0) + (DS_WRITE_B32 0, (EXTRACT_SUBREG $src0, sub0), $src1, $src1, 0, 0) >; /********** ================== **********/ |