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author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-14 23:24:53 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-14 23:24:53 +0000 |
commit | e8e33f448e8830590c498ac5101ef8b27446ca3b (patch) | |
tree | 2aada1408e415c2de01557c54d4804568f3bdd09 /lib/Target/R600 | |
parent | 68db37b952be497c94c7aa98cf26f3baadb5afd3 (diff) | |
download | external_llvm-e8e33f448e8830590c498ac5101ef8b27446ca3b.zip external_llvm-e8e33f448e8830590c498ac5101ef8b27446ca3b.tar.gz external_llvm-e8e33f448e8830590c498ac5101ef8b27446ca3b.tar.bz2 |
R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188430 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600')
-rw-r--r-- | lib/Target/R600/SIISelLowering.cpp | 2 | ||||
-rw-r--r-- | lib/Target/R600/SIInstrInfo.td | 2 | ||||
-rw-r--r-- | lib/Target/R600/SIInstructions.td | 2 | ||||
-rw-r--r-- | lib/Target/R600/SITypeRewriter.cpp | 16 |
4 files changed, 18 insertions, 4 deletions
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index 40f0827..30a510d 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -43,8 +43,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : addRegisterClass(MVT::i32, &AMDGPU::VSrc_32RegClass); addRegisterClass(MVT::f32, &AMDGPU::VSrc_32RegClass); - addRegisterClass(MVT::v1i32, &AMDGPU::VSrc_32RegClass); - addRegisterClass(MVT::f64, &AMDGPU::VSrc_64RegClass); addRegisterClass(MVT::v2i32, &AMDGPU::VSrc_64RegClass); addRegisterClass(MVT::v2f32, &AMDGPU::VSrc_64RegClass); diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index b741978..2639456 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -27,7 +27,7 @@ def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT", >; class SDSample<string opcode> : SDNode <opcode, - SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVec<1>, SDTCisVT<2, v32i8>, + SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>, SDTCisVT<3, i128>, SDTCisVT<4, i32>]> >; diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 4704217..e719cb3 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1326,7 +1326,7 @@ def : Pat < /* SIsample for simple 1D texture lookup */ def : Pat < - (SIsample v1i32:$addr, v32i8:$rsrc, i128:$sampler, imm), + (SIsample i32:$addr, v32i8:$rsrc, i128:$sampler, imm), (IMAGE_SAMPLE_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) >; diff --git a/lib/Target/R600/SITypeRewriter.cpp b/lib/Target/R600/SITypeRewriter.cpp index 9da11e8..f194d8b 100644 --- a/lib/Target/R600/SITypeRewriter.cpp +++ b/lib/Target/R600/SITypeRewriter.cpp @@ -16,6 +16,9 @@ /// legal for some compute APIs, and we don't want to declare it as legal /// in the backend, because we want the legalizer to expand all v16i8 /// operations. +/// v1* => * +/// - Having v1* types complicates the legalizer and we can easily replace +/// - them with the element type. //===----------------------------------------------------------------------===// #include "AMDGPU.h" @@ -109,6 +112,19 @@ void SITypeRewriter::visitCallInst(CallInst &I) { Types.push_back(i128); NeedToReplace = true; Name = Name + ".i128"; + } else if (Arg->getType()->isVectorTy() && + Arg->getType()->getVectorNumElements() == 1 && + Arg->getType()->getVectorElementType() == + Type::getInt32Ty(I.getContext())){ + Type *ElementTy = Arg->getType()->getVectorElementType(); + std::string TypeName = "i32"; + InsertElementInst *Def = dyn_cast<InsertElementInst>(Arg); + assert(Def); + Args.push_back(Def->getOperand(1)); + Types.push_back(ElementTy); + std::string VecTypeName = "v1" + TypeName; + Name = Name.replace(Name.find(VecTypeName), VecTypeName.length(), TypeName); + NeedToReplace = true; } else { Args.push_back(Arg); Types.push_back(Arg->getType()); |