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author | Tom Stellard <thomas.stellard@amd.com> | 2013-11-18 19:43:33 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2013-11-18 19:43:33 +0000 |
commit | ef37e453c407675ab5934d2f6bcec706b7810878 (patch) | |
tree | 949b61737c88b83dbd1e864781eeddd5aee7e178 /lib/Target/R600 | |
parent | b4c3516b0f7d879e332adf6f4dba3f4763c74086 (diff) | |
download | external_llvm-ef37e453c407675ab5934d2f6bcec706b7810878.zip external_llvm-ef37e453c407675ab5934d2f6bcec706b7810878.tar.gz external_llvm-ef37e453c407675ab5934d2f6bcec706b7810878.tar.bz2 |
R600: Add a SubtargetFeatture for disabling the ifcvt pass.
This is useful when writing test cases for the AMDIL structurizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195029 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600')
-rw-r--r-- | lib/Target/R600/AMDGPU.td | 5 | ||||
-rw-r--r-- | lib/Target/R600/AMDGPUSubtarget.cpp | 5 | ||||
-rw-r--r-- | lib/Target/R600/AMDGPUSubtarget.h | 2 | ||||
-rw-r--r-- | lib/Target/R600/AMDGPUTargetMachine.cpp | 3 |
4 files changed, 14 insertions, 1 deletions
diff --git a/lib/Target/R600/AMDGPU.td b/lib/Target/R600/AMDGPU.td index e9304c2..37ff6b1 100644 --- a/lib/Target/R600/AMDGPU.td +++ b/lib/Target/R600/AMDGPU.td @@ -28,6 +28,11 @@ def FeatureIRStructurizer : SubtargetFeature <"enable-irstructurizer", // Target features +def FeatureIfCvt : SubtargetFeature <"disable-ifcvt", + "EnableIfCvt", + "false", + "Disable the if conversion pass">; + def FeatureFP64 : SubtargetFeature<"fp64", "FP64", "true", diff --git a/lib/Target/R600/AMDGPUSubtarget.cpp b/lib/Target/R600/AMDGPUSubtarget.cpp index 1e21c8e..4e97e6e 100644 --- a/lib/Target/R600/AMDGPUSubtarget.cpp +++ b/lib/Target/R600/AMDGPUSubtarget.cpp @@ -37,6 +37,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : FP64 = false; CaymanISA = false; EnableIRStructurizer = false; + EnableIfCvt = true; ParseSubtargetFeatures(GPU, FS); DevName = GPU; } @@ -70,6 +71,10 @@ AMDGPUSubtarget::IsIRStructurizerEnabled() const { return EnableIRStructurizer; } bool +AMDGPUSubtarget::isIfCvtEnabled() const { + return EnableIfCvt; +} +bool AMDGPUSubtarget::isTargetELF() const { return false; } diff --git a/lib/Target/R600/AMDGPUSubtarget.h b/lib/Target/R600/AMDGPUSubtarget.h index c08cd6a..4288d27 100644 --- a/lib/Target/R600/AMDGPUSubtarget.h +++ b/lib/Target/R600/AMDGPUSubtarget.h @@ -50,6 +50,7 @@ private: bool FP64; bool CaymanISA; bool EnableIRStructurizer; + bool EnableIfCvt; InstrItineraryData InstrItins; @@ -66,6 +67,7 @@ public: bool hasHWFP64() const; bool hasCaymanISA() const; bool IsIRStructurizerEnabled() const; + bool isIfCvtEnabled() const; virtual bool enableMachineScheduler() const { return getGeneration() <= NORTHERN_ISLANDS; diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp index b19277d..9186c9d 100644 --- a/lib/Target/R600/AMDGPUTargetMachine.cpp +++ b/lib/Target/R600/AMDGPUTargetMachine.cpp @@ -169,7 +169,8 @@ bool AMDGPUPassConfig::addPreSched2() { if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) addPass(createR600EmitClauseMarkers(*TM)); - addPass(&IfConverterID); + if (ST.isIfCvtEnabled()) + addPass(&IfConverterID); if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) addPass(createR600ClauseMergePass(*TM)); return false; |