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| author | Brian Gaeke <gaeke@uiuc.edu> | 2004-03-04 04:37:22 +0000 |
|---|---|---|
| committer | Brian Gaeke <gaeke@uiuc.edu> | 2004-03-04 04:37:22 +0000 |
| commit | e7173b7e8ec1ac1bc4843dad84b0d84c3ad3e720 (patch) | |
| tree | 0cb14fd3a96b66fbef0ea7aef234e7435589a496 /lib/Target/Sparc | |
| parent | 2f3469013eb1b9f20c63a64cf60097ea99f093e7 (diff) | |
| download | external_llvm-e7173b7e8ec1ac1bc4843dad84b0d84c3ad3e720.zip external_llvm-e7173b7e8ec1ac1bc4843dad84b0d84c3ad3e720.tar.gz external_llvm-e7173b7e8ec1ac1bc4843dad84b0d84c3ad3e720.tar.bz2 | |
Floating point regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12110 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc')
| -rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.td | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index ccc3be6..b3f5a44 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -15,6 +15,10 @@ class Ri<bits<5> num> : Register { field bits<5> Num = num; // Numbers are identified with a 5 bit ID } +// Rf - 32-bit floating-point registers +class Rf<bits<5> num> : Register { + field bits<5> Num = num; // Numbers are identified with a 5 bit ID +} let Namespace = "V8" in { def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>; @@ -29,8 +33,15 @@ let Namespace = "V8" in { // Standard register aliases. def SP : Ri<14>; def FP : Ri<30>; - // Floating-point registers? - // ... + // Floating-point registers: + def F0 : Rf< 0>; def F1 : Rf< 1>; def F2 : Rf< 2>; def F3 : Rf< 3>; + def F4 : Rf< 4>; def F5 : Rf< 5>; def F6 : Rf< 6>; def F7 : Rf< 7>; + def F8 : Rf< 8>; def F9 : Rf< 9>; def F10 : Rf<10>; def F11 : Rf<11>; + def F12 : Rf<12>; def F13 : Rf<13>; def F14 : Rf<14>; def F15 : Rf<15>; + def F16 : Rf<16>; def F17 : Rf<17>; def F18 : Rf<18>; def F19 : Rf<19>; + def F20 : Rf<20>; def F21 : Rf<21>; def F22 : Rf<22>; def F23 : Rf<23>; + def F24 : Rf<24>; def F25 : Rf<25>; def F26 : Rf<26>; def F27 : Rf<27>; + def F28 : Rf<28>; def F29 : Rf<29>; def F30 : Rf<30>; def F31 : Rf<31>; } @@ -43,3 +54,7 @@ def IntRegs : RegisterClass<i32, 8, [G0, G1, G2, G3, G4, G5, G6, G7, O0, O1, O2, O3, O4, O5, O6, O7, L0, L1, L2, L3, L4, L5, L6, L7, I0, I1, I2, I3, I4, I5, I6, I7]>; + +def FPRegs : RegisterClass<f32, 4, [F0, F1, F2, F3, F4, F5, F6, F7, F8, + F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, + F23, F24, F25, F26, F27, F28, F29, F30, F31]>; |