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authorChris Lattner <sabre@nondot.org>2005-09-30 01:29:42 +0000
committerChris Lattner <sabre@nondot.org>2005-09-30 01:29:42 +0000
commit97d5e6461a28790fa341d9e3b58f043db549dc6a (patch)
tree00293d7848486e66ce181981b28822b890fc744a /lib/Target/SparcV8/SparcV8RegisterInfo.cpp
parentbf9716b9c48d3b0370c715cd79540945f73dc296 (diff)
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Pass extra regclasses into spilling code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23537 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SparcV8/SparcV8RegisterInfo.cpp')
-rw-r--r--lib/Target/SparcV8/SparcV8RegisterInfo.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
index de3fc80..af8605a 100644
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
@@ -40,7 +40,8 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) {
void SparcV8RegisterInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned SrcReg, int FrameIdx) const {
+ unsigned SrcReg, int FrameIdx,
+ const TargetRegisterClass *rc) const {
const TargetRegisterClass *RC = getClass(SrcReg);
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
@@ -59,7 +60,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
void SparcV8RegisterInfo::
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned DestReg, int FrameIdx) const {
+ unsigned DestReg, int FrameIdx,
+ const TargetRegisterClass *rc) const {
const TargetRegisterClass *RC = getClass(DestReg);
if (RC == V8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);