Rename the load and store opcodes. The non-fp ones only have one

variant worth worrying about; the fp ones have two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14362 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 2 insertions, 2 deletions

diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
index aa86e48..7b8cf0e 100644
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
@@ -33,7 +33,7 @@ int SparcV8RegisterInfo::storeRegToStackSlot(
   assert (RC == SparcV8::IntRegsRegisterClass
           && "Can only store 32-bit values to stack slots");
   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
-  BuildMI (MBB, I, V8::STrm, 3).addFrameIndex (FrameIdx).addSImm (0).addReg (SrcReg);
+  BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0).addReg (SrcReg);
   return 1;
 }
 
@@ -45,7 +45,7 @@ int SparcV8RegisterInfo::loadRegFromStackSlot(
 {
   assert (RC == SparcV8::IntRegsRegisterClass
           && "Can only load 32-bit registers from stack slots");
-  BuildMI (MBB, I, V8::LDmr, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
+  BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
   return 1;
 }