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authorBrian Gaeke <gaeke@uiuc.edu>2004-02-12 04:01:07 +0000
committerBrian Gaeke <gaeke@uiuc.edu>2004-02-12 04:01:07 +0000
commit17247c64f2511ca1aca2424f0208a6a0a1ec18c8 (patch)
tree5c42baa13d9356fff0120b37ddaf3bb185cfbea3 /lib/Target/SparcV9/RegAlloc
parent2d58f0691ec71f5c38b93c969c4bfdcd536491a8 (diff)
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Remove this MachineOpCodeFlags assertion - its test can never be false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11342 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SparcV9/RegAlloc')
-rw-r--r--lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp2
1 files changed, 0 insertions, 2 deletions
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 0cb1776..4a7d503 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -530,8 +530,6 @@ void PhyRegAlloc::updateMachineCode()
AddedInstrMap[DelaySlotMI].InstrnsAfter.size() > 0));
if (cond1 || cond2) {
- assert((MII->getOpCodeFlags() & AnnulFlag) == 0 &&
- "FIXME: Moving an annulled delay slot instruction!");
assert(delaySlots==1 &&
"InsertBefore does not yet handle >1 delay slots!");