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authorBrian Gaeke <gaeke@uiuc.edu>2004-08-18 20:04:24 +0000
committerBrian Gaeke <gaeke@uiuc.edu>2004-08-18 20:04:24 +0000
commit418379e229dc491050f7f6292aa8364c29b71301 (patch)
tree31de07aef8edcd0f8dfe0050513c5587dcace151 /lib/Target/SparcV9/RegAlloc
parente058b27faf9ba0df1582fddda55c3bcbd96de9a0 (diff)
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Instead of using isDummyPhiInstr, we just compare the opcode with V9::PHI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15906 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SparcV9/RegAlloc')
-rw-r--r--lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 2fd8e55..02f18fc 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -484,7 +484,7 @@ void PhyRegAlloc::updateMachineCode()
// their assigned registers or insert spill code, as appropriate.
// Also, fix operands of call/return instructions.
for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
- if (! TM.getInstrInfo()->isDummyPhiInstr(MII->getOpcode()))
+ if (MII->getOpcode() != V9::PHI)
updateInstruction(MII, MBB);
// Now, move code out of delay slots of branches and returns if needed.
@@ -552,7 +552,7 @@ void PhyRegAlloc::updateMachineCode()
MachineInstr *MInst = MII;
// do not process Phis
- if (TM.getInstrInfo()->isDummyPhiInstr(MInst->getOpcode()))
+ if (MInst->getOpcode() == V9::PHI)
continue;
// if there are any added instructions...