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| author | Alkis Evlogimenos <alkis@evlogimenos.com> | 2004-02-14 01:18:34 +0000 |
|---|---|---|
| committer | Alkis Evlogimenos <alkis@evlogimenos.com> | 2004-02-14 01:18:34 +0000 |
| commit | f81af21caf9c0f62c60b72762d9a927e8c24f679 (patch) | |
| tree | 6b7865d9540825fa4d391794ff356793a5dfc235 /lib/Target/SparcV9/RegAlloc | |
| parent | bc79471be19e412eed4d270908db7ac945be10ca (diff) | |
| download | external_llvm-f81af21caf9c0f62c60b72762d9a927e8c24f679.zip external_llvm-f81af21caf9c0f62c60b72762d9a927e8c24f679.tar.gz external_llvm-f81af21caf9c0f62c60b72762d9a927e8c24f679.tar.bz2 | |
Use newly added next() and prior() utility functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11430 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SparcV9/RegAlloc')
| -rw-r--r-- | lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp index cc019b4..a33d5c9 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp @@ -514,7 +514,7 @@ void PhyRegAlloc::updateMachineCode() for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII) if (unsigned delaySlots = TM.getInstrInfo().getNumDelaySlots(MII->getOpcode())) { - MachineBasicBlock::iterator DelaySlotMI = MII; ++DelaySlotMI; + MachineBasicBlock::iterator DelaySlotMI = next(MII); assert(DelaySlotMI != MBB.end() && "no instruction for delay slot"); // Check the 2 conditions above: @@ -552,8 +552,7 @@ void PhyRegAlloc::updateMachineCode() else { // For non-branch instr with delay slots (probably a call), move // InstrAfter to the instr. in the last delay slot. - MachineBasicBlock::iterator tmp = MII; - std::advance(tmp, delaySlots); + MachineBasicBlock::iterator tmp = next(MII, delaySlots); move2DelayedInstr(MII, tmp); } } @@ -646,8 +645,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR, // include all live variables before that branch or return -- we don't want to // trample those! Verify that the set is included in the LV set before MInst. if (MII != MBB.begin()) { - MachineBasicBlock::iterator PredMI = MII; - --PredMI; + MachineBasicBlock::iterator PredMI = prior(MII); if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpcode())) assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef) .empty() && "Live-var set before branch should be included in " |