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authorVikram S. Adve <vadve@cs.uiuc.edu>2001-10-28 21:41:46 +0000
committerVikram S. Adve <vadve@cs.uiuc.edu>2001-10-28 21:41:46 +0000
commita2a70946629ffaea6076cd57ef52845934e7a922 (patch)
tree7e38dd4eb9c923c3f3b090558e58d43787e2e6a1 /lib/Target/SparcV9/SparcV9InstrInfo.cpp
parentc7b2e5c81e01e3ca0d2325a156c20f82fd67400c (diff)
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Generate SETX for 64-bit integers!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1007 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SparcV9/SparcV9InstrInfo.cpp')
-rw-r--r--lib/Target/SparcV9/SparcV9InstrInfo.cpp36
1 files changed, 28 insertions, 8 deletions
diff --git a/lib/Target/SparcV9/SparcV9InstrInfo.cpp b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
index 6b6a406..318a944 100644
--- a/lib/Target/SparcV9/SparcV9InstrInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
@@ -24,22 +24,36 @@
static inline MachineInstr*
-CreateIntSetInstruction(int64_t C, bool isSigned, Value* dest)
+CreateIntSetInstruction(int64_t C, bool isSigned, Value* dest,
+ vector<TmpInstruction*>& tempVec)
{
MachineInstr* minstr;
+ uint64_t absC = (C >= 0)? C : -C;
+ if (absC > (unsigned int) ~0)
+ { // C does not fit in 32 bits
+ TmpInstruction* tmpReg =
+ new TmpInstruction(Instruction::UserOp1, NULL, NULL);
+ tempVec.push_back(tmpReg);
+
+ minstr = new MachineInstr(SETX);
+ minstr->SetMachineOperand(0, MachineOperand::MO_SignExtendedImmed, C);
+ minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, tmpReg,
+ /*isdef*/ true);
+ minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,dest);
+ }
if (isSigned)
{
minstr = new MachineInstr(SETSW);
minstr->SetMachineOperand(0, MachineOperand::MO_SignExtendedImmed, C);
+ minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, dest);
}
else
{
minstr = new MachineInstr(SETUW);
minstr->SetMachineOperand(0, MachineOperand::MO_UnextendedImmed, C);
+ minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, dest);
}
- minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, dest);
-
return minstr;
}
@@ -92,20 +106,24 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(Value* val,
bool isValidConstant;
int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
assert(isValidConstant && "Unrecognized constant");
- minstr = CreateIntSetInstruction(C, valType->isSigned(), dest);
+ minstr = CreateIntSetInstruction(C, valType->isSigned(), dest, tempVec);
minstrVec.push_back(minstr);
}
else
{
// Make an instruction sequence to load the constant, viz:
- // SETSW <addr-of-constant>, addrReg
+ // SETX <addr-of-constant>, tmpReg, addrReg
// LOAD /*addr*/ addrReg, /*offset*/ 0, dest
- // Only the SETSW is needed if `val' is a GlobalValue, i.e,. it is
+ // Only the SETX is needed if `val' is a GlobalValue, i.e,. it is
// itself a constant address. Otherwise, both are needed.
Value* addrVal;
int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
+ TmpInstruction* tmpReg =
+ new TmpInstruction(Instruction::UserOp1, val, NULL);
+ tempVec.push_back(tmpReg);
+
if (isa<ConstPoolVal>(val))
{
// Create another TmpInstruction for the hidden integer register
@@ -117,9 +135,11 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(Value* val,
else
addrVal = dest;
- minstr = new MachineInstr(SETUW);
+ minstr = new MachineInstr(SETX);
minstr->SetMachineOperand(0, MachineOperand::MO_PCRelativeDisp, val);
- minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,addrVal);
+ minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, tmpReg,
+ /*isdef*/ true);
+ minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,addrVal);
minstrVec.push_back(minstr);
if (isa<ConstPoolVal>(val))