The classes F4_3 and F4_4 have an `rd' operand that needs to be set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7073 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 3 insertions, 0 deletions

diff --git a/lib/Target/SparcV9/SparcV9_F4.td b/lib/Target/SparcV9/SparcV9_F4.td
index 2a2e467..981c9f0 100644
--- a/lib/Target/SparcV9/SparcV9_F4.td
+++ b/lib/Target/SparcV9/SparcV9_F4.td
@@ -80,11 +80,13 @@ class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1simm11rd {
 class F4_3<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
            string name> : F4_condcc {
   bits<5> rs2;
+  bits<5> rd;
 
   set op = opVal;
   set op3 = op3Val;
   set cond = condVal;
   set Name = name;
+  set Inst{29-25} = rd;
   set Inst{13} = 0; // i bit
   //set Inst{10-5} = dontcare;
   set Inst{4-0} = rs2;
@@ -99,6 +101,7 @@ class F4_4<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
   set op3  = op3Val;
   set cond = condVal;
   set Name = name;
+  set Inst{29-25} = rd;
   set Inst{13} = 1; // i bit
   set Inst{10-0} = sim11;
 }