Store instructions are different from other Format 3.1/3.2 instructions in that

they prefer the destination register to be last. Thus, two new classes were made
for them that accomodate for having this layout of operands (F3_1rd, F3_2rd).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6564 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 43 insertions, 7 deletions

diff --git a/lib/Target/SparcV9/SparcV9.td b/lib/Target/SparcV9/SparcV9.td
index 9575215..adc9e4d 100644
--- a/lib/Target/SparcV9/SparcV9.td
+++ b/lib/Target/SparcV9/SparcV9.td
@@ -603,15 +603,15 @@ def SRAXi6 : F3_13<2, 0b100111, "srax">;                 // srax r, shcnt64, r
 // Not currently used in the Sparc backend
 
 // Section A.52: Store Floating-point -p225
-def STFr  : F3_1<3, 0b100100, "st">;                      // st r, [r+r]
-def STFi  : F3_2<3, 0b100100, "st">;                      // st r, [r+i]
-def STDFr : F3_1<3, 0b100111, "std">;                     // std r, [r+r]
-def STDFi : F3_2<3, 0b100111, "std">;                     // std r, [r+i]
+def STFr  : F3_1rd<3, 0b100100, "st">;                      // st r, [r+r]
+def STFi  : F3_2rd<3, 0b100100, "st">;                      // st r, [r+i]
+def STDFr : F3_1rd<3, 0b100111, "std">;                     // std r, [r+r]
+def STDFi : F3_2rd<3, 0b100111, "std">;                     // std r, [r+i]
 
 // Not currently used in the Sparc backend
 #if 0
-def STQFr : F3_1<3, 0b100110, "stq">;                     // stq r, [r+r]
-def STQFi : F3_2<3, 0b100110, "stq">;                     // stq r, [r+i]
+def STQFr : F3_1rd<3, 0b100110, "stq">;                     // stq r, [r+r]
+def STQFi : F3_2rd<3, 0b100110, "stq">;                     // stq r, [r+i]
 #endif
 
 set isDeprecated = 1 in {
diff --git a/lib/Target/SparcV9/SparcV9_F3.td b/lib/Target/SparcV9/SparcV9_F3.td
index 1ba5a67..f29a3f8 100644
--- a/lib/Target/SparcV9/SparcV9_F3.td
+++ b/lib/Target/SparcV9/SparcV9_F3.td
@@ -62,12 +62,31 @@ class F3_rs2rd : F3_rs2 {
   set Inst{29-25} = rd;
 }
 
-// F3_rd - Common class of instructions that only have an rd field
+// F3_rd - Common class of instructions that have an rd field
 class F3_rd : F3 {
   bits<5> rd;
   set Inst{29-25} = rd;
 }
 
+// F3_rdrs1 - Common class of instructions that have rd and rs1 fields
+class F3_rdrs1 : F3_rd {
+  bits<5> rs1;
+  set Inst{18-14} = rs1;
+}
+
+// F3_rdrs1simm13 - Common class of instructions that have rd, rs1, and simm13
+class F3_rdrs1simm13 : F3_rd {
+  bits<13> simm13;
+  set Inst{12-0} = simm13;
+}
+
+
+// F3_rdrs1rs2 - Common class of instructions that have rd, rs1, and rs2 fields
+class F3_rdrs1rs2 : F3_rs1 {
+  bits<5> rs2;
+  set Inst{4-0} = rs2;
+}
+
 
 // Specific F3 classes...
 //
@@ -80,6 +99,15 @@ class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2rd {
   //set Inst{12-5} = dontcare;
 }
 
+// The store instructions seem to like to see rd first, then rs1 and rs2
+class F3_1rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
+  set op  = opVal;
+  set op3 = op3val;
+  set Name = name;
+  set Inst{13} = 0;   // i field = 0
+  //set Inst{12-5} = dontcare;
+}
+
 class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
   set op  = opVal;
   set op3 = op3val;
@@ -87,6 +115,14 @@ class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
   set Inst{13} = 1;   // i field = 1
 }
 
+// The store instructions seem to like to see rd first, then rs1 and imm
+class F3_2rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1simm13 {
+  set op  = opVal;
+  set op3 = op3val;
+  set Name = name;
+  set Inst{13} = 1;   // i field = 1
+}
+
 class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
   set op   = opVal;
   set op3  = op3val;