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authorRuchira Sasanka <sasanka@students.uiuc.edu>2001-09-15 19:11:31 +0000
committerRuchira Sasanka <sasanka@students.uiuc.edu>2001-09-15 19:11:31 +0000
commit866f1385b4144655a9ad09da54f6d810fcf181f9 (patch)
treea98054adff6173daa32210eaed7d702094331056 /lib/Target/SparcV9
parent6053b9337bedd7fdcdea3742199708d2f173d878 (diff)
downloadexternal_llvm-866f1385b4144655a9ad09da54f6d810fcf181f9.zip
external_llvm-866f1385b4144655a9ad09da54f6d810fcf181f9.tar.gz
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modified printing of debug messages
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@593 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SparcV9')
-rw-r--r--lib/Target/SparcV9/SparcV9Internals.h16
-rw-r--r--lib/Target/SparcV9/SparcV9RegInfo.cpp78
-rw-r--r--lib/Target/SparcV9/SparcV9TargetMachine.cpp27
3 files changed, 4 insertions, 117 deletions
diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h
index 43f67d3..87e4cd0 100644
--- a/lib/Target/SparcV9/SparcV9Internals.h
+++ b/lib/Target/SparcV9/SparcV9Internals.h
@@ -945,22 +945,12 @@ class UltraSparcRegInfo : public MachineRegInfo
return res;
}
-
-#if 0
- unsigned getRCIDOfMachineOp (const MachineOperand & Op) const {
-
- unsigned Type = getRegClassIDOfValue( Op.getVRegValue() );
-
- if( Op.getOperandType() == MachineOperand::MO_CCRegister )
- return Type + 2; // because of the order of CC classes
- else return Type;
+ // returns the register tha contains always zero
+ inline unsigned getZeroReg() {
+ return SparcIntRegOrder::g0;
}
-#endif
-
-
-
void colorArgs(const Method *const Meth, LiveRangeInfo& LRI) const;
static void printReg(const LiveRange *const LR) ;
diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp
index fe6ec23..0b30e5c 100644
--- a/lib/Target/SparcV9/SparcV9RegInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp
@@ -237,81 +237,3 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const
-
-
-
-
-#if 0
-
-//-----------------------------------------------------------------------------
-// Float Register Class
-//-----------------------------------------------------------------------------
-
-void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const
-{
-
- /* Algorithm:
- Record the color of all neighbors.
-
- Single precision can use f0 - f31
- Double precision can use f0 - f63
-
- if LR is a double, try to allocate f32 - f63.
- if the above attempt fails, or Value is single presion, try to allcoate
- f0 - f31.
-
- */
-
- unsigned NumNeighbors = Node->getNumOfNeighbors(); // total # of neighbors
-
- for(unsigned n=0; n < NumNeighbors; n++) { // for each neigh
- IGNode *NeighIGNode = Node->getAdjIGNode(n);
- if( NeighIGNode->hasColor() ) { // if neigh has a color
- IsColorUsedArr[ NeighIGNode->getColor() ] = true; // record that color
- if( NeighIGNode->getTypeID() == Type::DoubleTyID )
- IsColorUsedArr[ (NeighIGNode->getColor()) + 1 ] = true;
- }
- }
-
-
- unsigned SearchStart; // start pos of color in pref-order
- bool ColorFound= false; // have we found a color yet?
- unsigned c;
-
-
- if( Node->getTypeID() == Type::DoubleTyID ) { // if value is a double
-
- // search the double only reigon (f32 - f63)
- for( c=32; c < 64; c+= 2) {
- if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; }
- }
-
- // search f0 - f31 region
- if( ! ColorFound ) { // if color not found
- for( c=0; c < 32; c+= 2) {
- if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; }
- }
- }
-
- }
-
- else { // value is Single
-
- for( c=0; c < 32; c++) {
- if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; }
- }
- }
-
-
- if( ColorFound)
- Node->setColor(c); // first color found in preferred order
- else
- Node->markForSpill(); // no color found - must spill
-
-
- if( DEBUG_RA)
- UltraSparcRegInfo::printReg( Node->getParentLR() );
-
-}
-
-#endif
diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.cpp b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
index 2070af7..3e99980 100644
--- a/lib/Target/SparcV9/SparcV9TargetMachine.cpp
+++ b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
@@ -90,32 +90,7 @@ UltraSparcSchedInfo::initializeResources()
-//---------------------------------------------------------------------------
-// class UltraSparcRegInfo
-//
-// Purpose:
-// This class provides info about sparc register classes.
-//--------------------------------------------------------------------------
-
-#if 0
-UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc *const USI ) :
- UltraSparcInfo(USI),
- NumOfIntArgRegs(6),
- NumOfFloatArgRegs(6)
- {
- MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
- MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
- MachineRegClassArr.push_back( new SparcIntCCRegClass(IntCCRegClassID) );
- MachineRegClassArr.push_back( new SparcFloatCCRegClass(FloatCCRegClassID));
-
- assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 6 &&
- "6 Float regs are used for float arg passing");
- }
-
- // ***** TODO insert deletes for reg classes
-UltraSparcRegInfo::~UltraSparcRegInfo(void) { } // empty destructor
-#endif
//---------------------------------------------------------------------------
// UltraSparcRegInfo
@@ -427,7 +402,7 @@ UltraSparc::UltraSparc() : TargetMachine("UltraSparc-Native"),
optSizeForSubWordData = 4;
minMemOpWordSize = 8;
maxAtomicMemOpWordSize = 8;
- zeroRegNum = 0; // %g0 always gives 0 on Sparc
+ zeroRegNum = RegInfo.getZeroReg(); // %g0 always gives 0 on Sparc
}