Move MOTy::UseType enum into MachineOperand. This eliminates the

switch statements in the constructors and simplifies the
implementation of the getUseType() member function. You will have to
specify defs using MachineOperand::Def instead of MOTy::Def though
(similarly for Use and UseAndDef).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11715 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 64 insertions, 56 deletions

diff --git a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
index 0db45e3..f2368d6 100644
--- a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
+++ b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
@@ -422,7 +422,7 @@ uint64_t JITResolver::emitStubForFunction(Function *F) {
 
   // restore %g0, 0, %g0
   MachineInstr *R = BuildMI(V9::RESTOREi, 3).addMReg(g0).addSImm(0)
-                                            .addMReg(g0, MOTy::Def);
+                                            .addMReg(g0, MachineOperand::Def);
   SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*R));
   delete R;
 
diff --git a/lib/Target/SparcV9/SparcV9InstrSelection.cpp b/lib/Target/SparcV9/SparcV9InstrSelection.cpp
index c7bcdca..57f1251 100644
--- a/lib/Target/SparcV9/SparcV9InstrSelection.cpp
+++ b/lib/Target/SparcV9/SparcV9InstrSelection.cpp
@@ -786,9 +786,9 @@ CreateShiftInstructions(const TargetMachine& target,
   
   MachineInstr* M = (optArgVal2 != NULL)
     ? BuildMI(shiftOpCode, 3).addReg(argVal1).addReg(optArgVal2)
-                             .addReg(shiftDest, MOTy::Def)
+                             .addReg(shiftDest, MachineOperand::Def)
     : BuildMI(shiftOpCode, 3).addReg(argVal1).addZImm(optShiftNum)
-                             .addReg(shiftDest, MOTy::Def);
+                             .addReg(shiftDest, MachineOperand::Def);
   mvec.push_back(M);
   
   if (shiftDest != destVal) {
@@ -1119,11 +1119,11 @@ CreateCodeForVariableSizeAlloca(const TargetMachine& target,
 
     // Instruction 2: andn tmpProd, 0x0f -> tmpAndn
     getMvec.push_back(BuildMI(V9::ADDi, 3).addReg(tmpProd).addSImm(15)
-                      .addReg(tmpAdd15, MOTy::Def));
+                      .addReg(tmpAdd15, MachineOperand::Def));
 
     // Instruction 3: add tmpAndn, 0x10 -> tmpAdd16
     getMvec.push_back(BuildMI(V9::ANDi, 3).addReg(tmpAdd15).addSImm(-16)
-                      .addReg(tmpAndf0, MOTy::Def));
+                      .addReg(tmpAndf0, MachineOperand::Def));
 
     totalSizeVal = tmpAndf0;
   }
@@ -1141,7 +1141,7 @@ CreateCodeForVariableSizeAlloca(const TargetMachine& target,
 
   // Instruction 2: sub %sp, totalSizeVal -> %sp
   getMvec.push_back(BuildMI(V9::SUBr, 3).addMReg(SPReg).addReg(totalSizeVal)
-                    .addMReg(SPReg,MOTy::Def));
+                    .addMReg(SPReg,MachineOperand::Def));
 
   // Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
   getMvec.push_back(BuildMI(V9::ADDr,3).addMReg(SPReg).addReg(dynamicAreaOffset)
@@ -1534,7 +1534,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
 
         MachineInstr* retMI = 
           BuildMI(V9::JMPLRETi, 3).addReg(returnAddrTmp).addSImm(8)
-          .addMReg(target.getRegInfo().getZeroRegNum(), MOTy::Def);
+          .addMReg(target.getRegInfo().getZeroRegNum(), MachineOperand::Def);
       
         // If there is a value to return, we need to:
         // (a) Sign-extend the value if it is smaller than 8 bytes (reg size)
@@ -1581,11 +1581,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
           
           if (retType->isFloatingPoint())
             M = (BuildMI(retType==Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
-                 .addReg(retValToUse).addReg(retVReg, MOTy::Def));
+                 .addReg(retValToUse).addReg(retVReg, MachineOperand::Def));
           else
             M = (BuildMI(ChooseAddInstructionByType(retType), 3)
                  .addReg(retValToUse).addSImm((int64_t) 0)
-                 .addReg(retVReg, MOTy::Def));
+                 .addReg(retVReg, MachineOperand::Def));
 
           // Mark the operand with the register it should be assigned
           M->SetRegForOperand(M->getNumOperands()-1, retRegNum);
@@ -1751,7 +1751,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
         // Mark the register as a use (as well as a def) because the old
         // value will be retained if the condition is false.
         mvec.push_back(BuildMI(V9::MOVRZi, 3).addReg(notArg).addZImm(1)
-                       .addReg(notI, MOTy::UseAndDef));
+                       .addReg(notI, MachineOperand::UseAndDef));
 
         break;
       }
@@ -1786,7 +1786,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
         // value will be retained if the condition is false.
         MachineOpCode opCode = foldCase? V9::MOVRZi : V9::MOVRNZi;
         mvec.push_back(BuildMI(opCode, 3).addReg(opVal).addZImm(1)
-                       .addReg(castI, MOTy::UseAndDef));
+                       .addReg(castI, MachineOperand::UseAndDef));
 
         break;
       }
@@ -2149,12 +2149,12 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
         Value *lhs = subtreeRoot->leftChild()->getValue();
         Value *dest = subtreeRoot->getValue();
         mvec.push_back(BuildMI(V9::ANDNr, 3).addReg(lhs).addReg(notArg)
-                                       .addReg(dest, MOTy::Def));
+                                       .addReg(dest, MachineOperand::Def));
 
         if (notArg->getType() == Type::BoolTy) {
           // set 1 in result register if result of above is non-zero
           mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
-                         .addReg(dest, MOTy::UseAndDef));
+                         .addReg(dest, MachineOperand::UseAndDef));
         }
 
         break;
@@ -2180,12 +2180,12 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
         Value *dest = subtreeRoot->getValue();
 
         mvec.push_back(BuildMI(V9::ORNr, 3).addReg(lhs).addReg(notArg)
-                       .addReg(dest, MOTy::Def));
+                       .addReg(dest, MachineOperand::Def));
 
         if (notArg->getType() == Type::BoolTy) {
           // set 1 in result register if result of above is non-zero
           mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
-                         .addReg(dest, MOTy::UseAndDef));
+                         .addReg(dest, MachineOperand::UseAndDef));
         }
 
         break;
@@ -2210,12 +2210,12 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
         Value *lhs = subtreeRoot->leftChild()->getValue();
         Value *dest = subtreeRoot->getValue();
         mvec.push_back(BuildMI(V9::XNORr, 3).addReg(lhs).addReg(notArg)
-                       .addReg(dest, MOTy::Def));
+                       .addReg(dest, MachineOperand::Def));
 
         if (notArg->getType() == Type::BoolTy) {
           // set 1 in result register if result of above is non-zero
           mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
-                         .addReg(dest, MOTy::UseAndDef));
+                         .addReg(dest, MachineOperand::UseAndDef));
         }
         break;
       }
@@ -2262,7 +2262,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
             MachineOpCode movOpCode = ChooseMovpregiForSetCC(subtreeRoot);
             mvec.push_back(BuildMI(movOpCode, 3)
                            .addReg(subtreeRoot->leftChild()->getValue())
-                           .addZImm(1).addReg(setCCInstr, MOTy::UseAndDef));
+                           .addZImm(1)
+                           .addReg(setCCInstr, MachineOperand::UseAndDef));
                 
             break;
           }
@@ -2336,12 +2337,13 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
           mvec.push_back(BuildMI(V9::SUBccr, 4)
                          .addReg(leftOpToUse)
                          .addReg(rightOpToUse)
-                         .addMReg(target.getRegInfo().getZeroRegNum(),MOTy::Def)
-                         .addCCReg(tmpForCC, MOTy::Def));
+                         .addMReg(target.getRegInfo()
+                                   .getZeroRegNum(), MachineOperand::Def)
+                         .addCCReg(tmpForCC, MachineOperand::Def));
         } else {
           // FP condition: dest of FCMP should be some FCCn register
           mvec.push_back(BuildMI(ChooseFcmpInstruction(subtreeRoot), 3)
-                         .addCCReg(tmpForCC, MOTy::Def)
+                         .addCCReg(tmpForCC, MachineOperand::Def)
                          .addReg(leftOpToUse)
                          .addReg(rightOpToUse));
         }
@@ -2359,7 +2361,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
           // Mark the register as a use (as well as a def) because the old
           // value will be retained if the condition is false.
           M = (BuildMI(movOpCode, 3).addCCReg(tmpForCC).addZImm(1)
-               .addReg(setCCInstr, MOTy::UseAndDef));
+               .addReg(setCCInstr, MachineOperand::UseAndDef));
           mvec.push_back(M);
         }
         break;
@@ -2589,7 +2591,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
                 unsigned LoadOpcode = ChooseLoadInstruction(loadTy);
                 M = BuildMI(convertOpcodeFromRegToImm(LoadOpcode), 3)
                   .addMReg(regInfo.getFramePointer()).addSImm(tmpOffset)
-                  .addReg(argVReg, MOTy::Def);
+                  .addReg(argVReg, MachineOperand::Def);
 
                 // Mark operand with register it should be assigned
                 // both for copy and for the callMI
@@ -2668,11 +2670,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
               // -- For non-FP values, create an add-with-0 instruction
               if (argType->isFloatingPoint())
                 M=(BuildMI(argType==Type::FloatTy? V9::FMOVS :V9::FMOVD,2)
-                   .addReg(argVal).addReg(argVReg, MOTy::Def));
+                   .addReg(argVal).addReg(argVReg, MachineOperand::Def));
               else
                 M = (BuildMI(ChooseAddInstructionByType(argType), 3)
                      .addReg(argVal).addSImm((int64_t) 0)
-                     .addReg(argVReg, MOTy::Def));
+                     .addReg(argVReg, MachineOperand::Def));
               
               // Mark the operand with the register it should be assigned
               M->SetRegForOperand(M->getNumOperands()-1, regNumForArg);
@@ -2716,11 +2718,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
             // -- For non-FP values, create an add-with-0 instruction
             if (retType->isFloatingPoint())
               M = (BuildMI(retType==Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
-                   .addReg(retVReg).addReg(callInstr, MOTy::Def));
+                   .addReg(retVReg).addReg(callInstr, MachineOperand::Def));
             else
               M = (BuildMI(ChooseAddInstructionByType(retType), 3)
                    .addReg(retVReg).addSImm((int64_t) 0)
-                   .addReg(callInstr, MOTy::Def));
+                   .addReg(callInstr, MachineOperand::Def));
 
             // Mark the operand with the register it should be assigned
             // Also mark the implicit ref of the call defining this operand
@@ -2878,12 +2880,13 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
                                            tmpI, NULL, "maskHi2");
           mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpI)
                          .addZImm(8*(4-destSize))
-                         .addReg(srlArgToUse, MOTy::Def));
+                         .addReg(srlArgToUse, MachineOperand::Def));
         }
 
         // Logical right shift 32-N to get zero extension in top 64-N bits.
         mvec.push_back(BuildMI(V9::SRLi5, 3).addReg(srlArgToUse)
-                       .addZImm(8*(4-destSize)).addReg(dest, MOTy::Def));
+                         .addZImm(8*(4-destSize))
+                         .addReg(dest, MachineOperand::Def));
 
       } else if (destSize < 8) {
         assert(0 && "Unsupported type size: 32 < size < 64 bits");
diff --git a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
index 55db233..77aa098 100644
--- a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
+++ b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
@@ -74,7 +74,7 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
   int SP = TM.getRegInfo().getStackPointer();
   if (TM.getInstrInfo().constantFitsInImmedField(V9::SAVEi,staticStackSize)) {
     mvec.push_back(BuildMI(V9::SAVEi, 3).addMReg(SP).addSImm(C)
-                   .addMReg(SP, MOTy::Def));
+                   .addMReg(SP, MachineOperand::Def));
   } else {
     // We have to put the stack size value into a register before SAVE.
     // Use register %g1 since it is volatile across calls.  Note that the
@@ -86,21 +86,22 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
 			 SparcIntRegClass::g1);
 
     MachineInstr* M = BuildMI(V9::SETHI, 2).addSImm(C)
-      .addMReg(uregNum, MOTy::Def);
+      .addMReg(uregNum, MachineOperand::Def);
     M->setOperandHi32(0);
     mvec.push_back(M);
     
     M = BuildMI(V9::ORi, 3).addMReg(uregNum).addSImm(C)
-      .addMReg(uregNum, MOTy::Def);
+      .addMReg(uregNum, MachineOperand::Def);
     M->setOperandLo32(1);
     mvec.push_back(M);
     
     M = BuildMI(V9::SRAi5, 3).addMReg(uregNum).addZImm(0)
-      .addMReg(uregNum, MOTy::Def);
+      .addMReg(uregNum, MachineOperand::Def);
     mvec.push_back(M);
     
     // Now generate the SAVE using the value in register %g1
-    M = BuildMI(V9::SAVEr,3).addMReg(SP).addMReg(uregNum).addMReg(SP,MOTy::Def);
+    M = BuildMI(V9::SAVEr,3).addMReg(SP).addMReg(uregNum)
+          .addMReg(SP,MachineOperand::Def);
     mvec.push_back(M);
   }
 
@@ -148,7 +149,8 @@ void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
     {
       int ZR = TM.getRegInfo().getZeroRegNum();
       MachineInstr *Restore = 
-        BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0).addMReg(ZR, MOTy::Def);
+        BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0)
+          .addMReg(ZR, MachineOperand::Def);
       
       MachineCodeForInstruction &termMvec =
         MachineCodeForInstruction::get(TermInst);
diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp
index 8d6e6d5..33690f8 100644
--- a/lib/Target/SparcV9/SparcV9RegInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp
@@ -699,7 +699,7 @@ SparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
       MI = (BuildMI(V9::RDCCR, 2)
             .addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
                                       SparcIntCCRegClass::ccr))
-            .addMReg(DestReg,MOTy::Def));
+            .addMReg(DestReg,MachineOperand::Def));
     } else {
       // copy int reg to intCC reg
       assert(getRegType(SrcReg) == IntRegType
@@ -708,7 +708,8 @@ SparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
             .addMReg(SrcReg)
             .addMReg(SparcIntRegClass::g0)
             .addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
-                                      SparcIntCCRegClass::ccr), MOTy::Def));
+                                      SparcIntCCRegClass::ccr),
+                     MachineOperand::Def));
     }
     break;
     
@@ -718,15 +719,17 @@ SparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
     
   case IntRegType:
     MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum())
-      .addMReg(DestReg, MOTy::Def);
+      .addMReg(DestReg, MachineOperand::Def);
     break;
     
   case FPSingleRegType:
-    MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
+    MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg)
+           .addMReg(DestReg, MachineOperand::Def);
     break;
 
   case FPDoubleRegType:
-    MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
+    MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg)
+           .addMReg(DestReg, MachineOperand::Def);
     break;
 
   default:
@@ -800,7 +803,7 @@ SparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
     MI = (BuildMI(V9::RDCCR, 2)
           .addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
                                     SparcIntCCRegClass::ccr))
-          .addMReg(scratchReg, MOTy::Def));
+          .addMReg(scratchReg, MachineOperand::Def));
     mvec.push_back(MI);
     
     cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
@@ -860,29 +863,29 @@ SparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
   switch (RegType) {
   case IntRegType:
     if (target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset))
-      MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
-                                                                    MOTy::Def);
+      MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset)
+          .addMReg(DestReg, MachineOperand::Def);
     else
-      MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
-                                                                    MOTy::Def);
+      MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg)
+          .addMReg(DestReg, MachineOperand::Def);
     break;
 
   case FPSingleRegType:
     if (target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset))
-      MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
-                                                                    MOTy::Def);
+      MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset)
+          .addMReg(DestReg, MachineOperand::Def);
     else
-      MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
-                                                                    MOTy::Def);
+      MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg)
+          .addMReg(DestReg, MachineOperand::Def);
     break;
 
   case FPDoubleRegType:
     if (target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset))
-      MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
-                                                                    MOTy::Def);
+      MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset)
+          .addMReg(DestReg, MachineOperand::Def);
     else
-      MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
-                                                                    MOTy::Def);
+      MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg)
+          .addMReg(DestReg, MachineOperand::Def);
     break;
 
   case IntCCRegType:
@@ -893,7 +896,7 @@ SparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
           .addMReg(scratchReg)
           .addMReg(SparcIntRegClass::g0)
           .addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
-                                    SparcIntCCRegClass::ccr), MOTy::Def));
+                                    SparcIntCCRegClass::ccr), MachineOperand::Def));
     break;
     
   case FloatCCRegType: {
@@ -901,10 +904,10 @@ SparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
                                            SparcSpecialRegClass::fsr);
     if (target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset))
       MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
-        .addMReg(fsrRegNum, MOTy::UseAndDef);
+        .addMReg(fsrRegNum, MachineOperand::UseAndDef);
     else
       MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg)
-        .addMReg(fsrRegNum, MOTy::UseAndDef);
+        .addMReg(fsrRegNum, MachineOperand::UseAndDef);
     break;
   }
   default: