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author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-09-25 10:11:07 +0000 |
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committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-09-25 10:11:07 +0000 |
commit | c2b840cb7c58e59c68aaa589841c41fb272df66d (patch) | |
tree | b9ba05d65c96d6b7e9d32d3fa75caa9c4abeb45b /lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h | |
parent | 8ba3f9c9008223136207295b48b53c8aefffa178 (diff) | |
download | external_llvm-c2b840cb7c58e59c68aaa589841c41fb272df66d.zip external_llvm-c2b840cb7c58e59c68aaa589841c41fb272df66d.tar.gz external_llvm-c2b840cb7c58e59c68aaa589841c41fb272df66d.tar.bz2 |
[SystemZ] Add instruction-shortening pass
When loading immediates into a GR32, the port prefered LHI, followed by
LLILH or LLILL, followed by IILF. LHI and IILF are natural 32-bit
operations, but LLILH and LLILL also clear the upper 32 bits of the register.
This was represented as taking a 32-bit subreg of a 64-bit assignment.
Using subregs for something as simple as a move immediate was probably
a bad idea. Also, I have patches to add support for the high-word facility,
and we don't want something like LLILH and LLILL to stop the high word of
the same GPR from being used.
This patch therefore uses LHI and IILF to begin with and adds a late
machine-specific pass to use LLILH and LLILL if the other half of the
register is not live. The high-word patches extend this behavior to
IIHF, LLIHL and LLIHH.
No behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191363 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h')
-rw-r--r-- | lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h index 01ef093..84184af 100644 --- a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h +++ b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h @@ -47,6 +47,15 @@ namespace SystemZMC { extern const unsigned FP32Regs[16]; extern const unsigned FP64Regs[16]; extern const unsigned FP128Regs[16]; + + // Return the 0-based number of the first architectural register that + // contains the given LLVM register. E.g. R1D -> 1. + unsigned getFirstReg(unsigned Reg); + + // Return the given register as a GR64. + inline unsigned getRegAsGR64(unsigned Reg) { + return GR64Regs[getFirstReg(Reg)]; + } } MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII, |