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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-09-30 08:48:38 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-09-30 08:48:38 +0000 |
| commit | 514756983e9ba3684a89ed583bf5a98ffb20c203 (patch) | |
| tree | 924fc41da9747d8fbdccae0316eabbc2dc67629b /lib/Target/SystemZ/MCTargetDesc | |
| parent | 39004b537beb1acc26675c8943c2cce4ca8a0499 (diff) | |
| download | external_llvm-514756983e9ba3684a89ed583bf5a98ffb20c203.zip external_llvm-514756983e9ba3684a89ed583bf5a98ffb20c203.tar.gz external_llvm-514756983e9ba3684a89ed583bf5a98ffb20c203.tar.bz2 | |
[SystemZ] Rename 32-bit GPR registers
I'm about to add support for high-word operations, so it seemed better
for the low-word registers to have names like R0L rather than R0W.
No behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191655 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/MCTargetDesc')
| -rw-r--r-- | lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp index cb97bca..f17a621 100644 --- a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -28,10 +28,10 @@ using namespace llvm; const unsigned SystemZMC::GR32Regs[16] = { - SystemZ::R0W, SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, - SystemZ::R4W, SystemZ::R5W, SystemZ::R6W, SystemZ::R7W, - SystemZ::R8W, SystemZ::R9W, SystemZ::R10W, SystemZ::R11W, - SystemZ::R12W, SystemZ::R13W, SystemZ::R14W, SystemZ::R15W + SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, + SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, + SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, + SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L }; const unsigned SystemZMC::GR64Regs[16] = { |